ADC Channels Research Articles

Design of a very low power 12 bits, 40 MS/s ADC based on a time-interleaved SAR architecture

The paper describes a new figure of merit reachable in terms of very low power dissipation for a 12 bit, 40 MS/s Analog to Digital Converter in a 65 nm CMOS process with 1 V power supply. A differential time interleaved successive approximations register architecture is used. Each individual ADC channel is optimized with regard to power consumption hence interleaving 28 ADC channels in an analog memory like method, the total power consumption is only 280 μW including all the reference voltage drivers, the clock management and the digital sections. The total layout area of this converter is 0.87 mm2.

On-beam system test of the new readout electronics for the CMS Electromagnetic Calorimeter upgrade

Starting in 2029, the High Luminosity LHC (HL-LHC) at CERN is projected to achieve unparalleled instantaneous luminosity (7.5 × 1034 cm-2s-1) for an integrated luminosities of 4500 fb-1. To cope with the extreme conditions of 200 collisions per bunch crossing (pile-up), both on-detector and off-detector electronics of the CMS Electromagnetic Calorimeter (ECAL) will be upgraded. The new system will incorporate a dual-gain trans-impedance amplifier alongside an Application-Specific Integrated Circuit (ASIC) that includes dual 160 MHz ADC channels and features for gain selection and data compression. The lead tungstate crystals and avalanche photodiodes (APDs) will remain in service due to their proven reliability. To counteract the noise amplification in the APDs, attributed to radiation-induced dark currents, the operational temperature of the ECAL will be reduced from 18°C to roughly 9°C. Preliminary tests of these new electronics have yielded promising results. During tests beams at the CERN H4 beamline using an electron beam, the new electronics met both required energy resolution and linearity and achieved a timing resolution of 30 ps for energies above 50 GeV.

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS high granularity timing detector

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 °C shows negligible degradation over 16 days.

Upgrade of the CMS Barrel Electromagnetic Calorimeter for the High Luminosity LHC

The high luminosity upgrade of the LHC (HL-LHC) at CERN will provide unprecedented instantaneous and integrated luminosities of up to 7.5×1034 cm−2s−1 and 4500 fb−1, respectively, from 2029 onwards. To cope with the extreme conditions of up to 200 collisions per bunch crossing, and increased data rates, the on- and off-detector electronics of the CMS electromagnetic calorimeter (ECAL) will be replaced. A dual gain trans-impedance amplifier and an ASIC providing two 160 MHz ADC channels, gain selection, and data compression will be used. The lead tungstate crystals and avalanche photodiodes (APDs) in the current ECAL will keep performing well and will therefore be maintained. The noise increase in the APDs, due to radiation-induced dark currents, will be minimised by reducing the ECAL operating temperature from 18 °C to around 9 °C. Prototype HL-LHC electronics have been tested and have shown promising results. In two test beam periods using the CERN SPS H4 beamline and an electron beam, the new electronics achieved the target energy resolution and a timing resolution consistent that is consistent with our requirements of 30 ps timing for energies greater than 50 GeV.

A 14-bit 1.2-V low power SAR ADC with digital background calibration in 0.18 μm CMOS

A 14-bit successive-approximation-register analog-to-digital converter is proposed for intelligent sensing application. A redundant integer sub-radix-2 capacitor array is adopted to recover the conversion errors. The capacitor mismatch is further mitigated with the digital background calibration. Different from the previous calibration that requires two ADC channels, the calibration approach is based on a single ADC, resulting in a considerable area reduction. The input signal injected with two different values are successively quantized twice by this ADC, and then digital background calibration is performed with these two output data. Designed with a 0.18 μm CMOS technology, the proposed SAR ADC occupies an area of 0.5682 mm2. The design results indicate that the SAR ADC can achieve a signal-to-noise distortion ratio of 77.6 dB and a spurious-free dynamic range of 108.5 dB at the sampling rate of 125 kS/s with the capacitor mismatch of 5%. The power consumption is 24.1 μW and the corresponding figure of merit (FoM) is 71.0 fJ/Conversion-step at 1.2 V.

Digital demodulation method based on multichannel combined acquisition for near-infrared spectrometer

With the evolution of digital technology, the digital demodulation method has become widely employed in near-infrared (NIR) spectrometers due to its advantages of reducing the volume, enhancing the reliability, and increasing the flexibility of instruments. However, digital demodulation has a lower signal-to-noise ratio (SNR), which can be improved by lowering the measurement precision, speed, and stability. To improve the SNR without sacrificing the measurement speed or stability, an improved digital demodulation method was developed based on multichannel combined acquisition. To validate the proposed method, a multichannel combined acquisition digital lock-in amplifier demodulation system was designed for portable raster scanning NIR spectrometers. In this system, six ADC channels were used in conjunction to acquire the modulated sampling signal. Afterwards, comparative experiments were conducted to compare the conventional and novel methods. The experimental results revealed that the SNR increased from 2499 to 3007 with a measurement time of 16.75 s and 17.08 s, respectively. Furthermore, scanning the reference reflector resulted in a baseline drift of 0.064% and 0.060% with a scanning time of 128.27 s and 128.21 s. Scanning the kaolin sample resulted in a baseline drift of 0.27% and 0.23% with a scanning time of 128.44 s and 128.53 s. In brief, the multichannel combined acquisition method can improve the SNR of spectrometers without compromising their stability or measurement time.

CMS ECAL upgrade for precision timing and energy measurements at the High-Luminosity LHC

The High Luminosity upgrade of the LHC (HL-LHC) at CERN will provide unprecedented instantaneous luminosity of ∼5 × 1034 cm−2 s−1, leading to an average of 150–200 simultaneous collisions. This high instantaneous luminosity scenario presents a significant challenge for the detectors. The barrel region of the CMS electromagnetic calorimeter (ECAL) will be preserved but will be operated at a lower temperature and with a completely new readout and trigger electronics. A dual gain transimpedance amplifier and an ASIC providing two 160 MHz ADC channels, gain selection, and data compression will be used in the new readout electronics. The trigger decision will be moved off-detector and performed by powerful and flexible FPGA processors, allowing for more sophisticated trigger algorithms to be applied. The upgraded ECAL will be capable of high-precision energy measurements throughout HL-LHC and will greatly improve the time resolution for photons and electrons above 10 GeV. The performance obtained with the new electronics has been tested at CERN under an electron beam with a matrix of ECAL crystals equipped with APDs.

Pre-launch characterization of the spectrometer of Hard X-ray Imager (HXI) onboard the ASO-S mission

As one of the three payloads of the Advanced Space-based Solar Observatory (ASO-S), the pre-launch characterization of HXI includes the characterization of the collimator and the spectrometer. This article focuses on the pre-launch characterization of HXI's spectrometer, including detection efficiency, energy resolution, and energy to ADC channel (E-C) relationship. The detection efficiency characterization necessitates a sufficient number of calibrated energy points in the HXI observation energy range, with a refined measurement around the absorption edge of the lanthanum bromide crystal, and is calibrated with an X-ray beam. The characterization results are consistent with the simulations and show that the detection efficiency difference between detector modules is controlled within ±3%. Radioactive sources 133Ba and 137Cs are used to calibrate the energy resolution and E-C relationship. The characterization results show that all detector modules' energy resolutions are better than 26% at 32 keV, meeting the design specification. And their E-C relationships vary regularly with voltage. All of the characterization results indicate that the flight model of the HXI spectrometer meets the performance requirements and is capable of performing on-orbit observation activities.

The CMS electromagnetic calorimeter upgrade: high-rate readout with precise time and energy resolution

The electromagnetic calorimeter (ECAL) of the CMS detector has played an important role in the physics program of the experiment, delivering outstanding performance throughout data taking. The high-luminosity LHC will pose new challenges. The four to five-fold increase of the number of interactions per bunch crossing will require superior time resolution and noise rejection capabilities. For these reasons the electronics readout has been completely redesigned. A dual gain trans-impedance amplifier and an ASIC providing two 160 MHz ADC channels, gain selection, and data compression will be used in the new readout electronics. The trigger decision will be moved off-detector and will be performed by powerful and flexible FPGA processors, allowing for more sophisticated trigger algorithms to be applied. The upgraded ECAL will be capable of high-precision energy measurements throughout HL-LHC and will greatly improve the time resolution for photons and electrons above 10 GeV.

A miniature ultrasound M-Mode imaging system based on time delay spectrometry

For wearable ultrasound applications, power and safety are a concern. We have developed an imaging method based on time-delay spectrometry (TDS) that employs a low-voltage, wideband chirp to establish a relationship between reflector depth and frequency by mixing the transmit and receive signals. We will show a low power, 4 channel ultrasound M-Mode system capable of tracking in vivo muscle interfaces in the forearm. The battery powered imaging system consists of power regulation subsystem, a RF chirp subsystem, and four channels consisting of a transmit RF amplifier, a mixing unit, and a receive amplifier which are sampled at 40 KSPS by a processor with a four channel ADC. The processor performs an FFT on each demodulated return to get 4 scanlines that are tracked over time to produce M-Mode images that are sent to a host computer. The wearable system can provide M-Modes images of up to 4 cm in forearm at a framerate of 50 Hz for ∼7 h with a total power consumption of 1.92 W. We demonstrate the ability of a miniaturized TDS ultrasound imaging system to collect in-vivo M-Modes that can be used for long term monitoring. The system can be used for wearable applications due to its low power consumption. [United States Department of Defense, Congressionally Directed Medical Research Program, award number W81XWH-16-1-0722 (PI: S Sikdar). National Institute of Biomedical Imaging and Bioengineering of the National Institutes of Health under Award No. U01EB027601.]

Design of multi-channel digital correlator in SAMR

Synthetic Aperture Microwave Radiometer (SAMR) can be carried on the satellite to realize the global large-scale measurement of ocean salinity and soil moisture. As a key component of SAMR, the multi-channel digital correlator has been introduced in this paper from three aspects: an improved method to implement multi-channel correlation, the correlator design and the test results of the correlator. The improved method which effectively reduces the FPGA resource utilization and system complexity is applied to the multi-channel digital correlator system which consists of three signal collectors and one signal processor. The design of multi-channel digital correlator can ensure the real-time signal sampling and processing of 144 ADC channels. The results demonstrate that the measurement accuracy of correlation coefficient can exceed 0.99.

A Low-Processing-Rate Dual BPSK Tracking Method for BOC Modulated Signals

Among the existing wideband processing methods for binary offset carrier (BOC) signals, dual binary phase-shift keying (BPSK) tracking (DBT) features the interoperability with traditional BPSK tracking and flexible switching between single-sideband and wideband tracking modes. However, due to the large bandwidth of entire BOC signal, the DBT method requires a high signal sampling and processing rate, resulting in high computational burden. This letter proposes a low-processing-rate dual BPSK tracking (LPR-DBT) method to tackle this problem. A preprocessing unit is proposed to be added between the ADC and DBT correlator channels under the constraint of retaining the subcarrier ranging information. It converts both the upper and lower sidebands of BOC signal to near-zero frequency, respectively, and then decimates them. This significantly reduces the correlator channel processing rate without ranging performance loss. It is worth emphasizing that the delays and phase shifts introduced by the preprocessing to each sideband are carefully considered and dealt with to ensure the relationship between two sidebands required by the DBT method is not destroyed.

Calibration of the underground muon detector of the Pierre Auger Observatory

To obtain direct measurements of the muon content of extensive air showers with energy above 1016.5 eV, the Pierre Auger Observatory is currently being equipped with an underground muon detector (UMD), consisting of 219 10 m2-modules, each segmented into 64 scintillators coupled to silicon photomultipliers (SiPMs). Direct access to the shower muon content allows for the study of both of the composition of primary cosmic rays and of high-energy hadronic interactions in the forward direction. As the muon density can vary between tens of muons per m2 close to the intersection of the shower axis with the ground to much less than one per m2 when far away, the necessary broad dynamic range is achieved by the simultaneous implementation of two acquisition modes in the read-out electronics: the binary mode, tuned to count single muons, and the ADC mode, suited to measure a high number of them. In this work, we present the end-to-end calibration of the muon detector modules: first, the SiPMs are calibrated by means of the binary channel, and then, the ADC channel is calibrated using atmospheric muons, detected in parallel to the shower data acquisition. The laboratory and field measurements performed to develop the implementation of the full calibration chain of both binary and ADC channels are presented and discussed. The calibration procedure is reliable to work with the high amount of channels in the UMD, which will be operated continuously, in changing environmental conditions, for several years.

Low Power Self disabling Comparator for Asynchronous ADC

A low power single channel ADC with high sampling rate is designed in this work. The low power is accomplished by utilizing a self-disabling continuous time comparator those outcomes in less delay cells. The proposed ADC executed and simulated in 180nm CMOS technology. The possibility of 1.8 V supply in this technology provides improvement in step size and the improved delay cells yields increased sampling rate. The decision of asynchronous ADC is because of the way that it eliminates complicated correction methods to acquire better execution, as in flash, pipelined and SAR ADC. Asynchronous digital slope ADC, accomplishes power lower than the synchronous ADC. It does not need the complex alignment and can accomplish low power utilization.. So to improve speed of sampling, improvisation of delay cell and shortening of delay time is done. In this paper an improvised design of the StrongARM comparator having faster performance, smaller area, and higher power efficiency is designed.

An FPGA-based Direct Sampling and Digital Processing System for Wideband and Narrowband Radar Signal

This paper designs an integrated wideband and narrowband radar signal direct sampling and digital processing system based on FPGA. The system comprises a VPX case, a main board, a direct sampling board, a fiber board. It makes direct sampling of 1.8GHz-3.0GHz echo waves, with 3.2GHz sampling rate. The wideband and narrowband echo waves share the same ADC channel. After ADC sampling, both of wideband and narrowband data are exported to a mix-free digital quadrature demodulation module in FPGA. The narrowband data will be further processed by digital frequency down conversion. The wideband data will be further processed by digital de-chirp operation, with parallel DDS structure and multi-level decimation filters. Data rate of both the wideband and narrowband data after processing is decreased obviously. The designed sampling system cut down the analog radar signal processing operation, and decreases signal distortion. Besides, it integrated the reception, sampling and processing of wideband and narrowband signal, simplified the structure of radar system.

A time-interleaved pipelined ADC with ultra high speed sampling

Based on a standard 0.18μm BiCMOS process, a 12 bit 2GSps ADC is achieved using time-interleaved pipelined architecture in this work. The DC offset caused by the mismatch of ADC channels is removed due to the application of digital calibration technology, which improves the performance of the ADC. The power supply voltage is 1.8 V and the power consumption is 100 mW for each lane. The measurement results indicated that the circuit in this paper can be used in multi-channel time-domain interleaved pipelined ADC architecture to achieve a 2GSps ultra high speed ADC.

An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-Interleaved ADCs

Time-interleaving (TI) is a major trend for high-speed ADC designs. The major limitation of TI-ADC is the mismatches among ADC channels. Calibration techniques have been actively pursued to compensate the mismatches. In this paper, we present a new spectral calibration technique for TI-ADC. Although the technique does not run in the background, it does not need external calibration signals and has no constraint on the input signal, which is similar to blind estimation. Compared to benchmark designs, the new technique involves much less calibration hardware overhead, and calibrates all mismatches with much less time. In practice, this efficient technique can run repetitively to track the environment changes. It addresses the needs from practical TI-ADCs well. The technique is verified with extensive simulations on a 2GS/s 12-bit 16-channel ADC. With mismatch spurs over -40dBc, the technique can reliably suppress the spurs to be lower than -80dBc within about 4000 samples without the need of iteration.

CMS ECAL upgrade for precision timing and energy measurements at the High-Luminosity LHC

The High Luminosity upgrade of the LHC (HL-LHC) at CERN will provide unprecedented instantaneous and integrated luminosities of around 5×1034 cm−2s−1 and 3000 fb−1, respectively, from 2025 to 2035. During this operational period, an average of 140 to 200 collisions per bunch-crossing (pile up) is expected, posing a challenge to the event reconstruction. In order to cope with these extreme pile up conditions, harsh environment, and increased data rates, the Compact Muon Solenoid (CMS) detector is undergoing a radical Phase II upgrade program. In the barrel region of the CMS electromagnetic calorimeter (ECAL), the lead tungstate crystals and avalanche photodiodes (APDs) will keep performing well and will therefore be maintained, while the entire readout and trigger electronics will be replaced. A dual gain trans-impedance amplifier and an ASIC providing two 160 MHz ADC channels, gain selection, and data compression will be installed. The noise increase in the APDs, due to radiation-induced dark current, will be contained by reducing the temperature at which ECAL is operated. The trigger decision will be moved off-detector and performed by powerful and flexible FPGA processors, allowing for more sophisticated trigger algorithms to be applied. The upgraded ECAL will be capable of high-precision energy measurements and will greatly improve the time resolution for photons and electrons above 10 GeV. Together with the introduction of a new timing detector designed to perform timing measurements with the resolution of a few tens of picoseconds for minimum ionizing particles, the CMS detector will be able to precisely reconstruct the primary interaction vertex under the described pile up conditions.

Wideband Signal Analyzer Based on Time-Interleaved ADCs with Digital Calibration

This paper presents a novel architecture of wideband signal analyzer based on time-interleaved ADCs. Architecture of signal analyzer include improved method of digital calibration of ADC channels operating in the time-interleaved mode of input signals. This method is based on the least squares method. The advantage of the proposed method is high speed and high accuracy of ADC channels tuning in comparison with the majority of existing methods, which are based on the least squares method. The results of simulation modeling of the proposed method, including spectral analysis of the output signal before and after calibration, are presented. The comparison of the proposed method with existing methods is performed.

A digital phase-locked loop based LLRF system

TRIUMF’s ARIEL pre-buncher is powered by a sawtooth waveform which is the combination of 11.79 MHz, 23.57 MHz and 35.36 MHz harmonics. To upgrade the existing analog and digital hybrid LLRF control system, reduce the hardware cost, and achieve more flexible control of the system, an FPGA based digital daughter board is designed. The generation, control, and regulation of these three harmonics are all incorporated digitally inside a single FPGA. To reduce the number of RF interfaces on the motherboard, the new daughter board is designed to control the amplitude and phase of the sawtooth waveform with one channel ADC and DAC. To lock the output phase of the sawtooth waveform to the reference signal, a digital phase-locked loop is designed to lock all three harmonics to the external reference signal. The related work, including the system design of the LLRF control system and the development of the digital phase-locked loop, are presented in this paper.