Low Power Self disabling Comparator for Asynchronous ADC

Abstract

A low power single channel ADC with high sampling rate is designed in this work. The low power is accomplished by utilizing a self-disabling continuous time comparator those outcomes in less delay cells. The proposed ADC executed and simulated in 180nm CMOS technology. The possibility of 1.8 V supply in this technology provides improvement in step size and the improved delay cells yields increased sampling rate. The decision of asynchronous ADC is because of the way that it eliminates complicated correction methods to acquire better execution, as in flash, pipelined and SAR ADC. Asynchronous digital slope ADC, accomplishes power lower than the synchronous ADC. It does not need the complex alignment and can accomplish low power utilization.. So to improve speed of sampling, improvisation of delay cell and shortening of delay time is done. In this paper an improvised design of the StrongARM comparator having faster performance, smaller area, and higher power efficiency is designed.