Adaptive Look-up Table Research Articles

Anti-Windup Adaptive Look-Up Table Algorithms with Application to Data-Driven Engine Controls

Abstract This technical brief presents anti-windup adaptation algorithms for a look-up table, widely used in data-driven engine control systems to accurately model complex features while minimizing computational demand. Engine control systems are prone to uncertain variations due to aging, faults, and manufacturing tolerances, which can impact performance and emissions unless effectively managed. Therefore, there is a growing demand for adaptive features in these systems to maintain robust performance and emissions over their lifespan. This study develops computationally efficient adaptive look-up table algorithms using anti-windup recursive parameter estimation and covariance matrix resetting, ensuring robust and rapid adaptation under various operating conditions. The effectiveness of these algorithms is demonstrated through adapting an engine-out nitrogen oxides concentration map, which is crucial for tailpipe emission controls in compression-ignition engines.

Online Model Adaption for Energy Management in Fuel Cell Electric Vehicles (FCEVs)

The growing interest in low-impact mobility technologies has elevated the significance of fuel cell electric vehicles (FCEVs) in the automotive sector. Given the complexity of the resulting powertrain, the need for an effective energy management strategy (EMS) becomes essential to optimize efficiency and energy consumption in vehicles with diverse energy sources. Model-based control is the main approach to address the EMS in electrified vehicles. In particular, fuel cell power is commonly represented through a 1D look-up table using the current demand as input to simplify the implementation in a vehicle control unit. Uncertainties that may be implemented in maps due to simplifying hypotheses, dynamics, ageing, etc., can be propagated to powertrain control, motivating the adoption of adaptive look-up tables for FC modelling. In this study, an extended Kalman filter (EKF) is proposed to adapt the look-up table to actual FC behaviour by measuring its power and gradually correcting calibration errors, drift, and ageing. Subsequently, a standard equivalent consumption minimization strategy (ECMS) is employed to control the FCEV. The fuel cell model is calibrated with experimental data from an FCEV. The results demonstrate that the adaptive strategy outperforms the base calibration. Following an extensive simulation campaign, an improvement of 1.1% in fuel consumption was observed. Remarkably, after just one hour of operation, there was a notable 85% reduction in fuel cell power estimation error, even when the EMS was initially fed a biased look-up table.

A Modified Quantum-Inspired Genetic Algorithm Using Lengthening Chromosome Size and an Adaptive Look-Up Table to Avoid Local Optima

The quantum-inspired genetic algorithm (QGA), which combines quantum mechanics concepts and GA to enhance search capability, has been popular and provides an efficient search mechanism. This paper proposes a modified QGA, called dynamic QGA (DQGA). The proposed algorithm utilizes a lengthening chromosome strategy for a balanced and smooth transition between exploration and exploitation phases to avoid local optima and premature convergence. Apart from that, a novel adaptive look-up table for rotation gates is presented to boost the algorithm’s optimization abilities. To evaluate the effectiveness of these ideas, DQGA is tested by various mathematical benchmark functions as well as real-world constrained engineering problems against several well-known and state-of-the-art algorithms. The obtained results indicate the merits of the proposed algorithm and its superiority for solving multimodal benchmark functions and real-world constrained engineering problems.

Energy-efficient design techniques for LUT based adaptive digital pre-distorters

Energy-efficient design techniques for an adaptive Look-Up Table (LUT) based Digital Predistortion (DPD) system are presented. The proposed methods are simplification of the adaptation function, reduction of the memory hardware complexity and bypassing of the equalizer circuit. The equalizer circuit block is critical while the adaptation loop is enabled but need for this block while the loop is disabled is explored to reduce power dissipation. Three adaptation functions that require less complex hardware are presented. The system is modeled with Matlab-Simulink, then implemented using an FPGA and 130 nm ST-Silicon On Insulator (SOI) process. More than 33% of power saving is obtained by applying the proposed techniques and further power reductions are also possible by configuring the system.

Momentum boundary layers in transcritical channel flows

We present well-resolved large-eddy simulations (LES) of a channel flow solving the fully compressible Navier–Stokes equations in conservative form. An adaptive look-up table method is used for thermodynamic and transport properties. We apply a physically consistent subgrid-scale turbulence model, that is based on the Adaptive Local Deconvolution Method (ALDM) for implicit LES. The wall temperatures are set to enclose the pseudo-boiling temperature at a supercritical pressure, leading to strong property variations within the channel geometry. In total seven cases are computed covering different Reynolds numbers, pseudo-boiling positions and pressure values. The hot wall at the top and the cold wall at the bottom produce asymmetric mean velocity and temperature profiles which result in different momentum layer thicknesses. All cases feature a turbulent mass flux which is essential in turbulence modelling. Furthermore, we analyse the turbulent kinetic energy budgets, perform a quadrant and octant analysis of the Reynolds shear stress and employ an invariant map to study the anisotropy in transcritical turbulent channel flows.

A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> chirp slope, corresponding to 0.0002% of the chirp bandwidth.

Performance Analysis of Orthogonal Gradient Sign Algorithm Using Spline-based Hammerstein Model for Smart Application

This paper presents a spline-based Hammerstein model for adaptive filtering based on a sign algorithm with the normalised orthogonal gradient algorithm. Spline-based Hammerstein architecture consists of an interpolation spline-based adaptive lookup table in the part of nonlinear filter and an adaptive finite impulse response filter used in the part of linear filter. Hammerstein spline adaptive filter (HSAF) is a nonlinear filter for the nonlinear systems among the advantages in the low computational cost and high performance. An adaptive lookup table and spline control points are determined and derived with the orthogonal gradient-based mechanism. Performance analysis in terms of convergence properties and mean square analysis based on the mean square error (MSE) constraint are proven by using the Taylor series expansion of the estimation error in the form of the excess MSE. Experimental results indicate the robust performance of the proposed algorithm can provide the better performance than the other models based on the conventional least mean square Hammerstein spline adaptive filtering algorithm.

Slip-Clutch Torque Estimation via Real-Time Adaptive Lookup Table

Abstract Transfer case clutch is crucial in determining traction torque distribution between front and rear tires for four-wheel-drive (4WD) vehicles. Estimating time-varying clutch surface friction coefficient is critical for traction torque control since it is proportional to the clutch output torque. As a result, this paper proposes a real-time adaptive lookup table strategy to provide the time-varying clutch surface friction coefficient. Specifically, the clutch-parameter-dependent (such as clutch output torque and clutch touchpoint distance) friction coefficient is first estimated with available low-cost vehicle sensors (such as wheel speed and vehicle acceleration); and then a clutch-parameter-independent approach is developed for clutch friction coefficient through a one-dimensional lookup table. The table nodes are adaptively updated based on a fast recursive least-squares (RLS) algorithm. Furthermore, the effectiveness of adaptive lookup table is demonstrated by comparing the estimated clutch torque from adaptive lookup table with that estimated from vehicle dynamics, which achieves 14.8 Nm absolute mean squared error (AMSE) and 2.66% relative mean squared error (RMSE).

An Improved Hierarchical Control Structure for Robust Microgrid Operation and Seamless Mode Transfer under Linear and Nonlinear Loads conditions

This paper proposes the improved hierarchical- based control of Microgrid based on proportional and multi-resonance controllers to compensate for harmonic distortion of nonlinear loads. Moreover, the probable transition of MG, especially from grid-connected to unplanned islanding and unintentional MG resources outage are studied. In current and voltage controllers of three-phase VSIs which are located in the inner level, the proportional and multi-resonant controllers are implemented. To attain proper decoupled (P-Q) power-sharing, a selective harmonic type virtual impedance, and a droop-based control are implemented at the primary level. Next, to reach better restoration and subsequently, seamless transition in accidental islanding, unintentional MG-DG’s outage, and synchronization process, the advanced three-phase SRF-PLL with in-loop MAF along with a simple adaptive lookup table are implemented in the secondary level of control. The MATLAB/Simulink simulation results verified that the proposed method improved the performance of control, effectiveness, and robustness in upstream or local grid variation.

Large-eddy simulation of turbulent channel flow at transcritical states

We present well-resolved large-eddy simulations (LES) of a channel flow solving the fully compressible Navier–Stokes equations in conservative form. An adaptive look-up table method is used for thermodynamic and transport properties. A physically consistent subgrid-scale turbulence model is incorporated, that is based on the Adaptive Local Deconvolution Method (ALDM) for implicit LES. The wall temperatures are set to enclose the pseudo-boiling temperature at a supercritical pressure, leading to strong property variations within the channel geometry. The hot wall at the top and the cold wall at the bottom produce asymmetric mean velocity and temperature profiles which result in different momentum and thermal boundary layer thicknesses. Different turbulent Prandtl number formulations and their components are discussed in context of strong property variations.

A Multi-One Instruction Set Computer for Microcontroller Applications

This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to enable basic usability in microcontroller applications. The purpose of ${m}$ OISC is to enable simple data transfer tasks and run small programs while maintaining ultimate simplicity. We present the internal organization for a computer architecture including an 8bit I/O register, and 64kB central Random Access Memory (RAM), organized in two-bytes words. The processor can run code generated assuming an OISC or a Complex Instruction Set Computer (CISC) scheme (op-code based), depending on the programmer’s demands and based on the initial setting of a register during start-up. To enable practical applications and demonstrate successful exploitation of ${m}$ OISC in view of integration in a compiler back-end, we designed a custom Proof-of-Concept (PoC) software design toolchain based on LLVM and clang . Although not targeting all the features of commercial ISA, the toolchain is capable of compiling C code from LLVM intermediate representation or generating ${m}$ OISC code translated from ARM, x86, RISC-V, and MIPS assembly. The toolchain also enables practical Value Change Dump (VCD) simulations output with graphical plots of the CPU state and associated symbols. A PoC microcontroller system has been synthesized in a low power Field Programmable Gate Array (FPGA) and verified in a basic wireless telemetry application including a Synchronous Peripheral Interface (SPI) RFM9x Long RAnge (LoRA) transceiver and a MAX30205 Inter Integrated Circuit (I2C) temperature sensor, using its 8bit I/O port, with software bus interface implementation. ${m}$ OISC occupies ~6% of resources on a Cyclone 10LP FPGA, for 1397 Adaptive Look-Up Tables (ALUTs) and 461 dedicated logic registers. The measured dynamic current consumption of the complete FPGA board with synthesized ${m}$ OISC is 12mA at 100MHz clock.

Anti-Windup Recursive Least Squares Method for Adaptive Lookup Tables with Application to Automotive Powertrain Control Systems

Anti-Windup Recursive Least Squares Method for Adaptive Lookup Tables with Application to Automotive Powertrain Control Systems

In-FPGA Instrumentation Framework for OpenCL-Based Designs

The productivity achieved when developing applications on high-performance reconfigurable heterogeneous computing (HPRHC) systems is increased by using the Open Computing Language (OpenCL). However, the hardware produced by OpenCL compilers in field-programmable gate arrays (FPGAs) can result in severe performance bottlenecks that are challenging to solve. The problem is compounded by the fact that the generated netlist details are disorganized, making them mostly unreadable and only partially visible to designers. This paper proposes an in-FPGA instrumentation method and a new framework for extracting the FPGA-cycle-accurate timing performances of OpenCL-based designs. The results clearly show that the chosen execution model for OpenCL-based designs strongly affects the timing performance when it is not properly implemented. Our framework is implemented on an HPRHC platform that contains a CPU and two Arria10 FPGAs, and it is evaluated with a wide variety of benchmarks with different complexities. After testing on the reported benchmarks, the average logic overhead for one inserted instrument is 0.2 % of the total amount of adaptive look-up tables (ALUTs) and 0.1 % of the total registers in an FPGA. This resource utilization is between 1.5 and six times lower than those reported in the best previously published works. The scalability of the framework is also evaluated by inserting up to 50 instruments. The experimental results show that the average logic utilization per instrument is 0.19 % of the ALUTs and 0.17 % of the registers in the FPGA when 50 instruments are inserted.

New Adaptive Algorithm Development for Monitoring Aircraft Performance and Improving Flight Management System Predictions

To compute the most efficient route that the aircraft has to fly, the flight management system (FMS) needs a mathematical representation of the aircraft performance. However, after several years of operation, various factors can degrade the overall performance of the aircraft. Such degradation can affect the reliability of the aircraft model, and the crew would lose confidence in the fuel planning estimated by the FMS. This paper presents the results of a study in which a new adaptive algorithm is proposed for continuously updating the FMS performance model using cruise flight data. The proposed algorithm combines aircraft performance monitoring techniques with adaptive lookup tables to model the aerodynamic characteristics of the aircraft. The methodology was applied to the well-known Cessna Citation X business aircraft, for which a research aircraft flight simulator was available. The development of this methodology was accomplished by creating an initial performance model, adapting it using flight data in cruise, and finally comparing its prediction with a series of flight data collected with the flight simulator. Results have shown that the proposed methodology was able to reduce fuel flow prediction mean errors by about 5%, whereas the standard deviation was reduced by a factor of 3.4.

A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost.

A novel approach of multiplier design based on BCD decoder

&lt;p&gt;&lt;span&gt;A novel approach of multiplier design is presented in this paper. The design &lt;/span&gt;idea is implemented based on binary coded decimal (BCD) decoder to seven segment display, by computing all the probability of multiplying 3 3 binary digits bits and grouping in table rows. The obtaining of the combinational logic functions is achieved by simplified the generated columns of [A&lt;sub&gt;5: &lt;/sub&gt;A&lt;sub&gt;0&lt;/sub&gt;]&lt;sub&gt;, &lt;/sub&gt;using a Karnaugh map. Then, the 3 3-bits multiplier circuit is used to implement the 6x6- and 12x 12-bit multipliers. Comparing with a conventional multiplier, the proposed design outperformed in terms of the time delay by a 32% and 41.8% respectively. It is also reduced the combinational adaptive look-up-tables (ALUTs) by 24.6%, and 46% for both multipliers. Both overmentioned advantages make the proposed multipliers more attractive and suitable for high-speed digital systems&lt;/p&gt;&lt;p&gt; &lt;/p&gt;&lt;p&gt; &lt;/p&gt;&lt;p&gt; &lt;/p&gt;&lt;p&gt; &lt;/p&gt;&lt;p&gt; &lt;/p&gt;&lt;p&gt; &lt;/p&gt;

Sign Normalised Hammerstein Spline Adaptive Filtering Algorithm in an Impulsive Noise Environment

In this paper, a sign normalised least mean square algorithm (SNLMS) based on Hammerstein spline adaptive filter (HSAF) is proposed, which is derived by minimising the absolute value of the a posteriori error. The control points, collected in an adaptive lookup table which is interpolated by a local low-order polynomial spline curve and the tap weights of the linear filter are updated by using the direction information of the a posteriori error. The minimization of the absolute value of the a posteriori error reduces the impact of impulsive noises. The new algorithm is called HSAF-SNLMS and can be used to identify the Hammerstein-type nonlinear systems. Furthermore, the convergence performance analysis is carried out by considering the identification of the Hammerstein-type system and the computational complexity of the proposed algorithm is also analyzed. Simulation results in system identification demonstrate the proposed HSAF-SNLMS obtains more robust performance when compared with the existing spline adaptive filter algorithms in impulsive noise environments.

안테나 포인팅 에러를 고려한 ESIM이 FS 시스템에 미치는 간섭 영향 분석

CW (continuous wave) 도플러 레이다는 카메라와 달리 사생활 침해 문제를 해결할 수 있고, 비접촉 방식으로 신호를 얻을 수 있다는 장점이 있다. 따라서, 본 논문에서는 CW 도플러 레이다를 이용한 사람 행동 인식 시스템을 제안하고, 가속을 위한 하드웨어 설계 및 구현 결과를 제시한다. CW 도플러 레이다는 사람의 연속된 동작에 대한 신호를 측정한다. 이에, 동작 분류를 위한 단일 스펙트로그램을 얻기 위해 운동 동작의 횟수를 세는 기법을 제안하였다. 또한, 연산의 복잡도와 메모리 사용량을 최소화하기 위해 동작 분류에 BNN (binarized neural network)을 사용하였고, 검증 결과 94%의 정확도를 보임을 확인하였다. BNN의 복잡한 연산을 가속하기 위해 FPGA를 이용하여 BNN 가속기가 설계 및 구현되었다. 제안된 사람 행동 인식 시스템은 logic 7,673개, register 12,105개, combinational ALUT (adaptive look up table) 10,211개, block memory 18.7 Kb를 사용하여 구현되었으며, 성능 평가 결과 소프트웨어 구현 대비 연산 속도가 99.97% 향상되었다. Continuous wave (CW) Doppler radar has the advantage of being able to solve the privacy problem unlike camera and obtains signals in a non-contact manner. Therefore, this paper proposes a human activity recognition (HAR) system using CW Doppler radar, and presents the hardware design and implementation results for acceleration. CW Doppler radar measures signals for continuous operation of human. In order to obtain a single motion spectrogram from continuous signals, an algorithm for counting the number of movements is proposed. In addition, in order to minimize the computational complexity and memory usage, binarized neural network (BNN) was used to classify human motions, and the accuracy of 94% was shown. To accelerate the complex operations of BNN, the FPGA-based BNN accelerator was designed and implemented. The proposed HAR system was implemented using 7,673 logics, 12,105 registers, 10,211 combinational ALUTs, and 18.7 Kb of block memory. As a result of performance evaluation, the operation speed was improved by 99.97% compared to the software implementation.

Nonlinear active noise control using spline adaptive filters

A spline adaptive filter (SAF) based nonlinear active noise control (ANC) system is proposed in this paper. The SAF consists of a linear network of adaptive weights in cascade with an adaptive nonlinear network. The nonlinear network, in-turn consists of an adaptive look-up table followed by a spline interpolation network and forms an adaptive activation function. An update rule has been derived for the proposed ANC system, which not only updates the weights of the linear network, but also updates the nature of the activation function. An extensive simulation study has been conducted to evaluate the noise mitigation performance of the proposed scheme and the new method has been shown to provide improved noise cancellation efficiency with a lesser computational load in comparison with other popular ANC systems.

FPGA Implementation of Adaptive Digital Predistorter With Fast Convergence Rate and Low Complexity for Multi-Channel Transmitters

This paper reports an adaptive digital predistorter (DPD) with fast convergence rate and low complexity for multi-channel transmitters, which is fully implemented in a field programmable gate array. The design methodology and practical implementation issues are discussed, with concerns about the impact caused by carrier power shutdown and transmission power control. The proposed DPD is composed of multiple adaptive lookup table (LUT) units of uniform structures, allowing configurability for desired memory depth. A simplified multiplier-free normalized least mean square algorithm for fast adapting the LUT is introduced. The proposed DPD is also experimentally exploited to linearize a Doherty amplifier. The adjacent channel leakage ratio reaches -60 dB for both lower and upper bands in the test applying a long-term evolution signal. It is also demonstrated in this paper that the proposed DPD shows high robustness when a multi-channel global system for mobile communications signal with occasional carrier power shutdown is applied.