Adaptive Hold Logic Research Articles

Efficient Low-Power Timing-Error Control in Digital Integrated Circuits Using Timing Error-Tolerant Circuits and Time-Borrowing Techniques

In modern digital systems, real-time operation of integrated circuits is of paramount importance. Presently, a significant portion of energy consumption is attributed to the overhead incurred by accommodating worst-case scenarios. This research proposes an energy-efficient timing-error control method employing a circuit designed to tolerate timing errors. The critical path is adept at identifying and correcting timing errors, particularly those causing irregular data transitions following the rising edge of the clock. Management of the transparent window of the clock is instrumental in swiftly addressing timing faults using minimal logic. A novel time-borrowing technique is introduced to account for future errors, applicable to locations with a short flip-flop setup time. The timing mistake occurs in two stages, and during second stage, an organized clock ensures a sufficiently extended transparent window, allowing for preservation of regular data without necessitating alterations to system clock. The study utilizes Razor Flip-flop and Adaptive Hold Logic to detect and recover from timing issues. This low-power timing-error control method provides an efficient means of mitigating the energy overhead associated with worst-case scenario margins in real-time digital systems.

A Novel Paradigm to Eliminate Timing Violations using AHL

Objectives: This Paper presents a novel low power design approach for multipliers to eliminate timing violations. There are two major issues which are concentrated in this paper are positive bias temperature instability and negative bias temperature instability. Both the things affect the speed of transistor and leads to timing violations, which intern leads to the failure of an entire system. Methods: In this work, bypassing multiplier is used with adaptive hold logic. The implementation is done in 180 nm deep submicron CMOS technology. Findings: power consumption and error rate is studied after employing the AHL. Improvements: The experimental result shows that the performance of multipliers with AHL improved 72.8% when compared to existing methods and consumes less power.

Reliable High Performance Multiplier with Adaptive Hold Logic for Aging Awareness

Background: Digital multipliers, the most important part which is used to implement most of the digital processing and arithmetic applications such as Filters, FFT’s, etc. As the rapid developments in technology required, many researchers are going to design multipliers which offers an efficient design aspect with respect to the speed and power consumption. Statistical analysis: Multipliers are the key functional units in various applications. The transistor speed is reduced due to bias temperature instability effects. When this effect extends in distant future, the system may not work properly due to timing infraction. Findings: The overall performance of these systems depends on the multiplier’s throughput. The Negative Bias Temperature Instability (NBTI) effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), which results the increase in the threshold voltage of the pMOS transistor, hence the delay in the multiplier is increased. In the same way, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both the temperature effects decrease the transistor speed, in the long run, the system may fail due to timing violations. Usually consummation of a system depends on the throughput of the multiplier. So it is important to adopt a reliable high performance multiplier. The multiplier is able to attenuate the performance degradation due to aging. Improvement: Hence, the objective of the project is to design a high speed and power efficient multiplier to increase the performance of the device. Design of Multiplier circuit using Adaptive Hold Technique is proposed. By using AHT circuit we can reduce the NBTI and Positive Bias Temperature Instability(PBTI) effects, hence performance will be increased and the aging effects will be reduced. The proposed technique is done using Xilinx 14.7 tool. The code is simulated and synthesized and comparison results are made based on the performance of the multipliers with and without AHT.

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

ENGLISH

Digital multipliers are among the most arithmetic functional units in many applications, such as Fourier transform, discrete cosine transforms, and digital filtering. These applications depends on multipliers, if the multipliers are slow, the performance of entire circuits will be reduced. The proposed aging-aware multiplier design is implemented with a novel adaptive hold logic (AHL) circuit. The multiplier is based on variable-latency technique and adjust the AHL circuit to achieve reliable operation using NBTI and PBTI effects The AHL circuit can decide the input patterns require one or two cycles to adjust the judging criteria to ensure the minimum performance degradation after considerable aging occurs. Comprehensive analysis and comparison of the multipliers performance under different cycle periods to show the effectiveness of our proposed architecture. The performance in 16- and 32-bit multipliers, can be easily extended to large designs. It can provide reliable operations even after the aging effect occurs. The Razor flip-flops detect the timing violations and re-execute the operations using two cycles. The architecture will adjust the percentage of one-cycle patterns to minimize performance degradation due to the aging effect. When the circuit is aged, and many errors occur, the AHL circuit uses the second judging block to decide if an input is one or two cycles. The multiplier is adjust the AHL to mitigate performance degradation due to increase delay.

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> = -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a columnor row-bypassing multiplier. The experimental results show that our proposed architecture with 16 × 16 and 32 × 32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.

Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop

Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop