Adaptive CMOS Research Articles

Adaptive low-power CMOS LNA in internet of things based wireless sensor networks

With the increasing need for the Internet of things (IoT), wireless communication has become a popular technology for the network. This explosion of IoT wireless applications makes the power consumption a key metric in the design of wireless sensor nodes. The major constraint of the wireless sensors nodes is battery energy, which is the mainly challenging problem in designing IoT network. these constraints have imposed new yet stringent specs to the design of RF front-ends. The design of adaptive radio-frequency circuits, in order to reduce power consumption, is of interest. In a RF receiver chain, the Low Noise Amplifier (LNA) stand as critical elements on the power consumption.To address this purpose, this paper proposes a design strategy for an adaptive Low Noise Amplifier as the first element of the receiver chain. Hence the proposed LNA achieves the correct QoS for various scenario of communications. Using the proposed LNA, a significant trade-off between a conversion gain, noise figure and energy consumption is presented.

Time-of-Arrival Measurement Using Adaptive CMOS IR-UWB Range Finder With Scalable Resolution

This paper introduces an adaptive CMOS impulse-radio ultra-wideband (IR-UWB) range finder with scalable resolution for localization applications and presents a brief demonstration of its operation. The distance resolution of the proposed range finder can be adapted to the ranging environment using a two-step time-to-digital converter (TDC) with scalable delay cells. Using the scalable time resolution of the TDC, the proposed range finder can control its maximum detectable distance and range resolution without any change in hardware. The proposed CMOS IR-UWB range finder has been implemented with a 0.11- $\mu\text{m}$ process; the effective areas of the transmitter and receiver are 0.065 mm2 and 0.27 mm2, respectively. The range finder has a range 8 m, with 2.9 mm scalable resolution. The power consumptions of the transmitter and receiver are 1.5 mW and 42 mW, respectively.

A New Fully Differential Adaptive CMOS Line Driver Using Fuzzy Controller Suitable for ADSL Modems

In this paper, a new principle for an adaptive line driver using Fuzzy logic is presented. This type of line driver can adapt its output impedance and gain, automatically to the applied load using a fuzzy logic controller (FLC). This results in automatically corrected output impedance for different cables with terminations. Also, the line driver output impedance and gain become insensitive to process and line variations. As an example, a line driver for ADSL application has been designed. The circuit operates from a 3.3 v in a 0.35 um standard CMOS technology. The power consumption of FLC is about 1 mW. The circuit dissipates 106 mW and exhibits a -62 dB THD for a 3.2-Vpp signal at 5 MHz across a 75 ohms Load. It has a relatively high -3 dB bandwidth (240 MHz) with good phase margin of about 67 degrees in a 10 pF load capacitor.

A tone mapping algorithm for acquisition of high dynamic range images using event-driven adaptive digital CMOS pixels

An algorithm for the tone mapping of high dynamic range (HDR) scenes in digital CMOS pixels has been developed. The algorithm performs a content-aware compression over HDR scenes, which produces a representation of several decades of acquired data while keeping the main contents in the scene using only 7-bits/pixel.

Adaptive CMOS analog circuits for 4G mobile terminals—Review and state-of-the-art survey

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost.Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical.These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.

Prolog to adaptive CMOS: from biological inspiration to systems-on-a-chip

Prolog to adaptive CMOS: from biological inspiration to systems-on-a-chip

A differential 160-MHz self-terminating adaptive CMOS line driver

A wide-band differential line driver is presented for transformer-coupled cables integrated in standard 0.35-/spl mu/m CMOS. It achieves 160-MHz bandwidth and no loss in implementing the cable termination. While operating from a 3.3-V supply, the driver dissipates 155 mW and exhibits a -47.5-dB THD for a 2-V/sub pp/ signal across a 75-/spl Omega/ load. Automatically tuned termination and a voltage gain independent of process and load impedance variation are provided by the architecture.

A CMOS two-path tree search detector

Two-path tree search (TPTS) is a detection algorithm combining a decision-feedback equalizer and a two-path tree search estimator. This sub-optimal tree search overcomes the exponential increase in hardware complexity with tree length in a fixed-delay tree search structure. An adaptive mixed-signal CMOS TPTS detector is presented in this paper. The integrated circuit occupies 2.77 mm by 2.44 mm (including the bonding pads) in a 0.6 /spl mu/m CMOS process. It performs about 0.8 dB better than a conventional decision-feedback equalization for a disk drive read channel.