Adaptive Charge Pump Research Articles

An optimization method for PLL‐based charge control SIMO Buck DC‐DC

SummaryThe PLL‐based charge control scheme is optimized and implemented in a single‐inductor multiple‐output (SIMO) Buck DC‐DC in this paper. In order to decrease cross regulation (CR) during heavy load transient, the gain adaptive charge pump (GACP) is optimized to speed up the regulation of inductor current, and the current loop off‐time (CLOT) control is introduced to prevent the PLL‐based structure from frequency unlock. The proposed SIMO is designed in a 0.18 μm standard CMOS process. Experimental results show that the worst CR performance is 0.026 mV/mA, which is a 50% improvement of PLL‐based charge control scheme and 61.19% advantage above the existing charge‐controlled SIMO.

A 39.5-dB SNR, 300-Hz Frame-Rate, 56 × 70-Channel Read-Out IC for Electromagnetic Resonance Touch Panels

In this paper, a pen detection analog system for an electromagnetic resonance (EMR) touch panel is presented. An adaptive charge pump is proposed in the transmitter to drive a high current to the EMR panel and achieve a high signal-to-noise ratio (SNR) in the receiver. To compensate for the mismatches between the channels due to fabrication variations of the EMR panels and process variations of the analog front-ends (AFEs), a transmitter driver with an adaptive controller is proposed, and an AFE calibration is implemented in the transmitter and the receiver, respectively. Also, a 9-bit, 2-MS/s time-interleaved flash successive-approximation-register (SAR) analog-to-digital converter (ADC) with 3-bit flash and 6-bit SAR ADCs is proposed to increase the frame rate with small area and power consumption. External noises, such as display and charger noises, can be rejected by the differential processing, analog low-pass filter, and digital filters in the digital signal processor (DSP). This read-out integrated circuit is implemented in a 0.18-μm Bipolar-CMOS-DMOS (BCD), and the die area is ${\text{40 mm}}^{\text{2}}$ including DSP and ADCs. The power consumptions are 110 and 45 mW in the transmitter and receiver modes, respectively. The SNR is about 39.5 dB and the frame rate is about 300 Hz in the 56 × 70 touch panel.

High-Efficiency Charge Pump LED Driver Circuit Design

In this paper, Using CSMC 0.5μm CMOS process to design each sub-module, the circuit simulation, and adjustment and validation of parameters have been carried out by simulation tools. The low static power and high conversion efficiency charge pump LED driver circuit has been designed. The circuits nucleus module is adaptive charge pump (1x/1.5x/2x charge pump), to converse a wider range of input voltage to a constant output voltage with high efficiency. This circuit only needs some external capacitors, and dont need inductor. So it reduces EMI electromagnetic interference and application cost, etc.

Efficient Energy Harvesting With Electromagnetic Energy Transducers Using Active Low-Voltage Rectification and Maximum Power Point Tracking

This paper reports on efficient interfacing of typical vibration-driven electromagnetic transducers for micro energy harvesting. For this reason, an adaptive charge pump for dynamic maximum power point tracking is compared with a novel active full-wave rectifier design. For efficient ultra-low voltage rectification, the introduced active diode design uses a common-gate stage in conjunction with supply-independent biasing. While this active rectifier offers low voltage drops, low complexity and ultra-low power consumption, the adaptive charge pump allows dynamic maximum power point tracking with implicit voltage up-conversion. Hence, efficient energy harvesting with high-resistive transducers, e.g., electromagnetic generators, becomes possible even at buffer voltage levels far above actual transducer output voltages. Both interfaces are fully-integrated in a standard 0.35 μm twin-well CMOS process. The designs are optimized for sub-mW transducer power levels and wide supply voltage ranges. Thus, these presented transducer interfaces are particularly suitable for compact micro energy harvesting systems, such as wireless sensor nodes or medical implants. The active diode rectifier achieves efficiencies over 90% at a wide range of input voltage amplitudes of 0.48 V up to 3.3 V. The adaptive charge pump can harvest with a total efficiency of close to 50%, but very independent of the actual buffer voltage. This charge pump starts operating at a supply voltage of 0.8 V, and has an input voltage range of 0.5 V-2.5 V . Finally, results of harvesting from an actual electromagnetic generator prototype are presented.

A 1.2 V Power Supply, 2.43 Times Power Efficient, Adaptive Charge Pump Circuit with Optimized Threshold Voltage at Each Pump Stage for Ferroelectric-NAND Flash Memories

A 1.2 V power supply adaptive charge pump for the low voltage and low power ferroelectric (Fe)-NAND flash memory is proposed. The proposed circuit is fabricated with the complementary metal–oxide–semiconductor (CMOS) compatible ferroelectric-gate field-effect transistors (FeFETs) process for Fe-NAND flash memories. By using FeFETs as diodes in the charge pump and optimizing the threshold voltage (VTH) of FeFETs at each pump stage, the power efficiency of the charge pump circuit to generate the program voltage increases from 21.7 to 52.7% without the circuit area and the process step penalty. The VTH optimization of FeFETs is realized by repeating the program and the monitor operations during the testing after the fabrication. During the testing, the power efficiency is monitored to detect the optimal VTH which maximizes the power efficiency at each pump stage. FeFETs in proposed circuits are immune to the disturb and a highly reliable circuit operation is experimentally demonstrated.

A Ferroelectric NAND Flash Memory for Low-power and Highly Reliable Enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V Low-power CPU and SoC

AbstractThis paper overview recent research results about ferroelectric FETs such as a Ferroelectric (Fe-) NAND flash memory for enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V operation low-power CPU and SoC.In the last five years, as the data through internet increases, the power consumption at the data center doubled. To solve the power crisis SSD is expected to replace HDD. For such an enterprise SSD, the Fe-NAND flash memory is most suitable due to a low power consumption and a high reliability. The Fe-NAND is composed of Metal Ferroelectric Insulator Semiconductor transistors. The program/erase voltage decreases from 20V to 6V. In the Fe-NAND, the electric polarization in the ferroelectric layer flips with a lower electric field and the Vth of a memory cell shifts. Due to a low program/erase voltage, a low power operation is achieved. In the Fe-NAND, a high write/erase endurance, 100Million cycle, four orders of magnitudes higher than the conventional NAND, is realized because there is no stress-induced leakage current.The Fe-NAND flash memory with a non-volatile (NV) page buffer is also proposed. The data fragmentation of SSD in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. In addition, a zero Vth memory cell scheme is proposed to best optimize the reliability of the Fe-NAND. The Vth shift caused by the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. A 1.2V operation adaptive charge pump circuit for the low voltage and low power Fe-NAND is introduced. By using Fe-FETs as diodes in the charge pump and optimizing the Vth of Fe-FETs at each pump stage, the power efficiency and the output voltage increase by 143% and 25% without the circuit area and process step penalty.Finally, a ferroelectric 6T-SRAM is proposed for the 0.5V operation low power CPU and SoC. During the read/hold, the Vth of Fe-FETs automatically changes to increase the static noise margin by 60%. During the stand-by, the Vth increases to decrease the leakage current by 42%. As a result, the supply voltage by 0.11V, which decreases the active power by 32%.

A PLL clock frequency multiplier using dynamic current matching adaptive charge-pump and VCO frequency reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (VCO) is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time.

Design of a CMOS adaptive charge pump with dynamic current matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25 μm 2.5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matehing characteristics regardless of the charge pump output voltages.