Active Neutral Point Clamped Research Articles

Low-Complexity Dual-Vector Model Predictive Control for Single-Phase Nine-Level ANPC-Based Converter

This article proposes a dual-vector finite-control-set model predictive control (FCS-MPC) with reduced complexity for a novel nine-level active neutral point clamped (ANPC) converter. This topology considerably reduces the used number of power switches compared to other topologies. Only nine power switches and two flying capacitors (FCs) are used to generate nine voltage levels. The proposed MPC scheme notably reduces the computational burden by directly locating the best two vectors without the need for multiple evaluations of the cost function as in the conventional method. Using one weighting factor in the cost function, three objectives are considered, namely, current tracking, FCs voltage control, and dc-link stabilization, reducing the heavy effort of coordinating weighting factors. Mathematical analyzes were carried out to determine the optimal duration of the selected voltage vectors. While the sequence of the two voltage vectors is identified based on the total harmonic distortion (THD) definition to minimize its value. Compared with standard FCS-MPC, lower steady-state errors, lower THDs, better harmonic distribution, and shorter execution times are achieved. The proposed MPC method is validated and compared with other prior-art control methods through experimental implementation.

Dead-Time Compensation in Active NPC Three-Level Inverters Considering Current Ripple

Existence of dead time that makes the ultimate terminal voltage being inconsistent with the modulation voltage, is recognized as the main reason for leading output voltage distortion, as well as the corresponding low-frequency current harmonics through the filter inductance in inverters. The distortion becomes particularly severe in high power-density high efficiency applications where the wide bandgap semiconductors are gradually being adopted, providing higher switching frequency with small junction capacitance. In order to explain this phenomenon, the mechanism of three-phase current distortion in the vicinity of phase current zero-crossing point is thoroughly studied by vector analysis in the space-vector (SV) plane. The relevant factors that lead to the degradation of current quality are also summarized. Improved compensation strategy has been proposed to ameliorate the current distortion. Compared with the conventional method, an additional item for current ripple compensation is introduced, the value of which is obtained by the deadbeat predictive method. This simple scheme avoids the compensation error caused by current ripple and significantly reduces the current total harmonic distortion (THD) value under the case of small inductance. Furthermore, neutral-point (NP) potential balance control is also considered in conjunction with the scheme. Simulations and experiments are carried out in an active NP clamped (ANPC) inverter platform, which demonstrates the validity of theoretical analysis and the proposed method.

Performance analysis and control of a novel 7‐level active neutral point clamped (ANPC) topology

AbstractThis paper introduces a novel 7‐level active neutral‐point clamped (ANPC) switched capacitor multilevel inverter (SCMLI) with voltage‐boosting capabilities. The proposed converter can produce seven levels and a voltage boosting of 1.5 times with a single dc source. For boosting the voltage, two self‐balanced switched capacitors and two dc link capacitors with active neutral point are used with nine switches. For controlling the output voltage, the level‐shifted modulation technique and modified nearest level control technique is used. The performance of the converter is evaluated with both modulation techniques. The operation of the proposed SCMLI and the design of capacitors for the proposed circuit is discussed in detail. The proposed topology can eliminate the leakage current and has reduced voltage stress across switches which makes it suitable for solar photovoltaic applications. The proposed converter is compared with some other recently introduced converters in terms of voltage gain, the number of components used, and the voltage stress across the switches. For verifying the performance of the proposed circuit, the experimental and simulation results are presented in the paper. The experimental results closely agree with the simulation and theoretical studies. The total harmonic distortion (THD) in the output voltage and efficiency is compared with both modulation techniques.

Low-Complexity Finite Set Model Predictive Control for Split-Capacitor ANPC Inverter With Different Levels Modes and Online Model Update

In this article, an improved finite-control-set model predictive control (FCS-MPC) is presented for an active neutral point clamped (ANPC) topology. The considered converter significantly reduces the required power electronics components compared with other common dc-link converters, where only seven active switches, one bidirectional switch, and two floating capacitors (FCs) are employed to produce nine levels in the phase voltage. The developed FCS-MPC handles three control objectives with only one weighting factor, namely, current control, FC balancing, and NP potential stabilization, which reduces the cumbersome effort required for weighting factors coordination. In addition, the number of iterations required to identify the optimal vector is significantly reduced, which, in turn, reduces the execution time of the algorithm. The proposed control method empowers the considered converter to operate in different modes under the faulty condition of the bidirectional switch without any structure modification, which guarantees continuous operation of the converter while ensuring the balancing of FCs and dc-link capacitors in all operating modes. The sensitivity of the proposed FCS-MPC to parameter mismatch, which is a basic issue of MPC-based techniques, is tackled by employing an extended Kalman filter (EKF) to online estimate the system parameters. The proposed FCS-MPC algorithm is experimentally validated and compared with the conventional FCS-MPC method under different operating conditions.

Fault Analysis and Clearance in FL-APC DC–AC Converter

The traditional active neutral-point-clamped (APC) dc–ac converter maintains great common-mode voltage with high-frequency (CMV-HF) reduction capability, so it has limited voltage gain. This article presents a new five-level APC (FL-APC) dc–ac converter capable of voltage step-up in a single-stage inversion. In the suggested design, a common ground not only reduces the CMV-HF but also improves dc-link voltage usage. While comparing with traditional two-stage FL-APC dc–ac converter, the proposed design has lower voltage stresses and greater uniformity. While improving overall efficiency, the suggested clamped dc–ac converter saves three power switches and a capacitor. Modeling and actual tests have proven the suggested APC inverter’s overall operation, efficacy, and achievability. The proposed circuit is finally tested with fault clearance capability.

A Seven-Level Inverter With Natural Balance and Boosting Capability

This paper introduces a new active-neutral-point clamped (ANPC) seven-level inverter with a switched-capacitor technique. The introduced inverter generates a seven-level ac output voltage with a maximum voltage-boosting gain of 1.5. The higher output voltage does not imply high voltage across the switches, as the maximum blocking voltage of the switches does not exceed the input voltage. The dc-link capacitor voltages are naturally balanced, and the flying capacitor achieves self-balancing through the series-parallel connection of the input voltage source, without the need for auxiliary control methods. Additionally, compared to major traditional seven-level inverters such as NPC, FC, and hybrid topologies, the proposed topology reduces the dc voltage requirement by 33.3%, eliminating the need for an intermediate dc-boosting stage and making the introduced inverter a good candidate for applications such as photovoltaic panels and full-cells systems, both characterized by a low input voltage. The operation and performance of the proposed topology are validated through simulation and experimental results.

An intelligent technique for fault detection and localization of three-level ANPC inverter with NP connection for electric vehicles

An intelligent technique for detecting and localizing an inverter switch fault or phase fault of a Three-Level Active Neutral Point Clamped (ANPC) inverter is proposed in this research. Moreover, a 3L-ANPC inverter can gain the controllability of EV's power train and not need to be stalled even after the occurrence of the fault. Hence, an efficient fault diagnosis methodology is required to identify the type of phase fault by a Support Vector Machine (SVM), a machine learning model consisting of sets of labeled training data with regression and classification challenges. Finally, when the fault occurs, the location of the switch fault can be identified by a Deep Neural Network (DNN), which consists of layers of neurons between the input and output layers which fuses the feature extraction process with increased accuracy. Thus, the detection and localization of the open-circuit fault of the switches in the ANPC inverter help overcome all single faults, hence gaining its current controllability without stopping the vehicle. The accuracy of fault detection is improved in a precise manner. Finally, the performance of the proposed work is evaluated over other conventional models concerning varied metrics like the accuracy of identification and localization.

Matrix-Based Approach for Open-Circuit Fault-Tolerant Analysis and PWM Design of Active Neutral-Point-Clamped Converters

Active neutral-point-clamped converter adds open-circuit fault-tolerant (OCFT) capability compared with the widely used original neutral-point-clamped (NPC) topology. However, such capability is hard to utilize due to difficulties in pulse-width modulation (PWM) design and the randomness of failure points, particularly in high-level converters. Current research mainly focused on low-level topologies with a limited number of fault scenarios; moreover, the analysis and design are performed in a nonsystematic way. In this article, the OCFT operations of active NPC (ANPC) converters with multiple fault switches are investigated and the systematic PWM design process is proposed. First, different matrices are proposed for the ANPC converters to capture the complicated topology information and achieve an exhaustive analysis of the topological redundancy. Then, a step-by-step process is proposed to derive the suitable OCFT PWM patterns. The five-level ANPC converter is investigated as an example. Its experimental results validate that the proposed approach can 1) properly predict the behavior of converters systematically so that the tolerable faults and intolerable can be identified during the design procedure, and 2) the inherent fault-tolerant capability of the five-level ANPC converter can be guaranteed through the proposed method, and 3) multiswitch open-circuit faults can be easily dealt with by implementing suitable carrier-based PWM schemes.

Advanced PWM Techniques for Multi-Level Inverters With a Multi-Level Active CM Noise Filter

Pulsewidth modulation (PWM)-based power electronics inverters are being widely used for various applications, including motor drives. However, the common-mode voltage (CMV) resulting from switching operations in the PWM inverters causes significant performance degradation of the system and can cause potential damage to motors. Since the effects of the CMV can be more severe in wide bandgap (WBG) and high switching frequency-based converter systems, various methods have been proposed to mitigate the CM noise issues. This work presents a multi-level inverter system composed of a multi-level inverter with a proposed multi-level active power filter (APF). For attenuating the CMV in multi-level inverters using multi-carrier-based PWM methods, a novel PWM method is presented for the proposed multi-level APF. The three-phase five-level active-neutral-point-clamped (ANPC) II-type inverter using the apparent switching frequency doubling (ASFD) PWM is used as an example of the multi-level inverters and carrier-based PWM methods to analyze and verify the proposed CMV attenuation method. The APF generates and injects the APF voltage equal to the CMV to attenuate the CM noise accurately. Various key challenges, including the dead-time compensation, are addressed through the proposed advanced PWM techniques to improve the CMV attenuation performance. Simulation and experimental results are provided to verify the comparison and effectiveness of the proposed CMV attenuation method.

A Self-Voltage Balanced Hybrid Three-Level MV Inverter Using 3.3-kV SiC MOSFET Module With False-Trigger-Proof Design

This article presents a self-voltage balanced three-level (3L) active-neutral-point-clamped (ANPC) medium-voltage (MV) inverter. Two switches of this inverter operate at high frequency (HF), while four switches operate at low frequency (LF), which is suitable to be implemented with hybrid “Si IGBTs + SiC MOSFETs” for MV applications. A 3.3-kV SiC MOSFET power module with low parasitic packaging is applied as HF switches, and the dc-link capacitor voltages can be self-balanced through periodic charging/discharging processes with a small decoupling capacitor. However, the inrush current occurs during voltage balancing processes, resulting in the false trigger of desat protection for LF switches. In this article, the mechanism of inrush current during voltage balancing processes is analyzed and a 3L gate driving method is proposed for LF switches to solve the false-triggering issue and improve the inrush energy loss distribution. In addition, high dv/dt of SiC switching transients may cause the false-triggering issue of HF switches, and desat protection design equations are therefore derived for this 3.3-kV SiC MOSFET power module to achieve a fast (< 440 ns) short-circuit response and maintain a good noise immunity to high dv/dt. A 4-kV dc, 40-kVA inverter prototype is built in the laboratory and the experimental results are provided to verify the proposed methods.

A new design of active NPC converter topology with higher voltage gain for solar PV applications

In the low voltage applications, the high gain multilevel inverters has seen more visibility due to the improved harmonic profile with multilevel voltage as well as boosting feature. A boost active neutral point clamped (ANPC) multilevel inverter (MLI) configuration with reduced resource count has been proposed in this paper. The proposed MLI produces 11 levels (11L) voltage with the help of 12 switches of blocking voltage ratings lesser than the peak value of output voltages. For attaining the boosting of 2.5 in output voltage, 4 capacitors are used in the proposed MLI which are inherently self-balanced. The capacitors charging as well as discharging are done by implementing the simple logic of parallel/series connection with the active power DC source. The proposed MLI is implemented and tested in the laboratory at various operating conditions, and the corresponding results and discussion are presented.

A Highly Efficient Si-/SiC-Based Hybrid Active NPC Converter With a Novel Modulation Scheme

With the increasing demand for high-performance power electronic systems, the semiconductor device utilization has gained significant importance. This article proposes the Si/SiC devices based active neutral-point-clamped converter comprising SiC-based H-bridge structure. A novel pulsewidth modulation (PWM) scheme is also proposed that results in an effective utilization of the switching devices. In the proposed converter, the Si devices are soft-switched for all power-factor loading conditions. Therefore, high efficiency can be obtained even at high switching frequency operation with wide range of power factor values. Further, the conduction losses of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s are minimized by strategically selecting the switching states in such a way that the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s conduct in parallel conduction paths during the null state operation. This leads to further enhanced efficiency. This article presents the detailed operating principle of the proposed topology operated with the presented PWM scheme. Moreover, a device loss analysis is presented to evaluate the conduction and switching losses of the proposed topology. The presented experimental results validate the performance parameters of the proposed topology with the proposed PWM scheme. Finally, the proposed PWM scheme is compared with the existing PWM schemes using efficiency values of the proposed and some of the prominent existing converter configurations.

A hybrid high‐efficiency nine‐level inverter with high DC voltage utilization ratio

AbstractThis paper proposes a new hybrid nine‐level inverter topology with high efficiency and high dc voltage utilization ratio, which provides a potential for renewable energy power conversion. The proposed inverter can synthesize up to nine voltage levels with only ten switching devices and a flying capacitor (FC). To improve the operation efficiency, a hybrid‐device topology based on Si and SiC is proposed. The total device cost of this inverter is much lower than the all‐SiC‐based inverter. Compared with other advanced multilevel inverters, a notable feature is the more comprehensive performance of the proposed inverter. In addition to having fewer components and higher efficiency, the dc voltage utilization ratio of the inverter is 2.5 times that of the traditional inverter such as Neutral Point Clamped (NPC), FC, and Active NPC (ANPC). A hybrid FC voltage balancing strategy based on redundancy switching states and three voltage levels step switching method is implemented to reduce FC voltage ripple. Besides, a cooperative voltage control strategy between the dc‐link capacitors and FC ensures the neutral‐point voltage balancing. The voltage stresses analysis and the design guidelines of components are discussed in detail. A comparison with some existing topologies has also been made to highlight its performance. Experimental results verify the validity of the proposed inverter topology and the control schemes.

High-Frequency GaN-Based ANPC Three-Level Converter as a Low-Noise Arbitrary PWL Voltage Generator

Recent advances in the technology of gallium nitride (GaN) power devices and high-frequency magnetic materials are key enablers of small, compact designs of power electronic converters in the megahertz range and the power range up to several hundreds of watts. However, impact of different switch modulation strategies along with the devices and magnetic materials must be carefully characterized to fully understand the boundaries of current technology and to be able to exploit it fully. This is usually performed through a holistic, automated design procedure based on multiobjective optimization which focuses on the converter efficiency and power density for the given electrical parameters. In this article, an optimized 100-W, 1.75-MHz switching frequency, four-quadrant, piecewise linear (PWL) arbitrary voltage generator based on active neutral-point-clamped (ANPC) three-level converter is presented. Diversity of modulation techniques for the hard-switched ANPC converter suitable for high-frequency (HF) applications are revisited, and impact on switching losses is characterized in detail. The generator is capable of providing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm {\mathrm {100}}~\text {V}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm {\mathrm {1}}~\text {A}$ </tex-math></inline-formula> at the output, with tracking speeds up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\text {V/}\mu \text {s}$ </tex-math></inline-formula> and steady-state efficiency above 95% with a physical size less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12~\text {cm}^{2}$ </tex-math></inline-formula> . Thermal management of the system is successfully resolved using advanced cooling plates based on pyrolytic graphite sheets (PGSs) and forced air convection. Having these characteristics, the presented generator outperforms the existing linear and hybrid power amplifiers (LPA/HPA) from the literature.

A Three-Phase Five-Level Inverter With High DC Voltage Utilization and Self-Balancing Capacity of Floating Capacitor

Multilevel inverter are popular solutions in photovoltaic power station, wind farm, and other renewable energy generation. This article presents a three-phase five-level inverter with high dc voltage utilization. A significant feature of the inverter is that its maximum dc voltage utilization is twice that of the traditional three-phase inverters such as neutral point clamped, flying capacitor (FC), cascaded H-bridge, and active NPC. What is more, the inverter can realize the self-starting and self-balancing of the FC, and the self-balancing of the dc-link capacitors, so the complex FC voltage balancing strategy and bus midpoint voltage control method are not needed anymore. The voltage and current stresses analysis and the design guidelines of components are discussed in detail. A comparison with some existing topologies has also been made to highlight its performance. Taking one phase as an example, both the simulations and experiments are carried out to verify the validity of the proposed inverter and modulation strategy.

Common-Mode Current Analysis and Cancellation Technique for Dual Active Bridge Converter Based DC System

This article presents an active neutral point clamped (ANPC)-based parallel dual-active bridge (DAB) architecture which combines <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> cancellation and power sharing in order to reduce electromagnetic interference (EMI) caused by common-mode (CM) current. High <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> associated with wide bandgap devices causes high CM current mainly due to parasitic capacitances. The corresponding conducted EMI can remarkably reduce the reliability of power converters and other onboard systems. This issue becomes worse due to higher dc bus voltage trend in electric vehicles (EV) and other dc systems. Conventional techniques struggle to provide attenuation in a wide frequency range. The problem can also be severe in soft-switched DAB converters as they operate at relatively higher frequencies. In this article, initially, an in-depth theoretical analysis is provided to understand the complimentary <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> events. Various factors causing nonideal <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> cancellation are discussed in detail together with possible solutions. Detailed experimental results are obtained from a 1100 V–150 V parallel DAB system including both the high and low voltage sides at different <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> rates. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> cancellation at lowered <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> rates facilitated by power sharing and small snubbers provide up to 25 dBuA reduction in CM conducted EMI. A comparison with CM chokes is also presented to validate improved attenuation in a wide frequency range.

An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid

Abstract Renewable energy generation systems connected to utility grid require perfect synchronization to grid which is one of the most important issues that needs to be taken into consideration. This paper proposed a hardware-accelerated implementation for the decoupled double synchronous reference frame phase-locked loop (DDSFR-PLL) for grid synchronization in grid-connected converters in weak grid that suffers from phase voltage-unbalance, variable phase and frequency conditions. Since the transformations and filtering of this method is computationally intensive and needs to be executed as fast as possible by the microcontroller unit (MCU) and Due to the presence of other current and voltage regulation loops in the same interrupt service routine (ISR) with high frequency rate, a hardware-based acceleration using the STM32G4x4 MCU built-in filter, filter math accelerator (FMAC) and coordinate rotation digital computer (CORDIC) is used to speed the execution time. This study addresses the description, derivation and implementation of the both DQ-PLL and DDSRF-PLL algorithms. The performance of both pure-software and accelerated implementation is demonstrated, compared and run on a three-level active neutral point clamped (ANPC) converter board. In proposed method, CPU load dropped from 80.5% by using the conventional software implementation to 23.6% (70% load reduction).This reduction in CPU load enables the addition of more features and more advanced current and voltage control algorithms.

Optimized Switching Strategy for ANPC–DAB Converter Through Multiple Zero States

Multilevel circuits can achieve high-voltage level, power density, and performance. This article considers a dual active bridge (DAB) based on the active neutral-point-clamped (ANPC) three-level circuit (ANPC–DAB). The soft-switching characteristics of the ANPC circuit during the switching process between switching states are analyzed, and the conditions for enabling all 12 switching devices to achieve zero-voltage switching (ZVS) on all the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> switching transitions are obtained. Based on this, the distribution of hard-switching turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> and conduction losses of power devices is further analyzed, and an optimized switching strategy that can balance the loss distribution of power devices is proposed by the evaluation of all zero states and analysis of a switching-state sequence. Moreover, this article examines the effect of the proposed switching strategy by analyzing the loss distribution of power devices and efficiency of the ANPC–DAB. Finally, experiments are conducted using a 1-kW prototype. The simulation and experimental results show that the proposed switching strategy can effectively improve the loss distribution of power devices while all the power devices realize ZVS.

Operation and Efficiency Analysis of a Five-Level Single-Phase Hybrid Si/SiC Active Neutral Point Clamped Converter

The ability to improve both the size and efficiency of multilevel single-phase converters is a key to uplift them as an attractive solution for industries, while the high number of switches and complex modulation techniques understandably make them unattractive. Five-level active neutral point clamped (ANPC) converter, due to its inherent advantages such as employing different switching frequencies and using different switch technologies, presents an ideal candidate for study. This article performs a comprehensive analysis of the converter to highlight the advantages of it. This analysis results in a modified hybrid modulation that effectively regulates the neutral point (NP) of the dc link. Consequently, the combination of the topology and the modified modulation make the converter ideal to utilize two different switch technologies—in this article, silicon carbide (SiC) and Si MOSFET. To evaluate the analysis and the effectiveness of modulation, a 2-kW hybrid five-level ANPC is built. The converter current behavior is analyzed to determine the power loss in the filter and switches. The efficiency measurement is performed and compared with the calculated efficiency. There is a close coherency between the measurement and the calculated results and a peak efficiency of 98.4% is achieved.

Enhanced Level-Shifted Modulation for a Three-Phase Five-Level Modified Modular Multilevel Converter (MMC)

The rapid growth of the penetration level of renewable energy sources (RESs) in low-voltage (LV) networks increases the research interest in more efficient, compact, reliable, and easily expandable energy conversion systems. The long commutation loops of the existing LV multilevel converters (MLCs), such as active neutral point clamped (ANPC) converters, lead to high-voltage overshoots induced during switching due to the significant parasitic inductance. Modular multilevel converters (MMCs) are gaining an increased interest due to their modularity, flexibility, and short commutation loops also for some LV applications. However, several issues related to the number of components, dc capacitor requirements, and the added complexity need to be considered. This article aims to reduce the five-level modified MMC capacitance requirements where the upper and lower submodules (SMs) are connected in parallel. This reduction has been achieved using an improved modulation technique by minimizing the insertion time of the SMs that require higher capacitance. The proposed modulation is effective in reducing the inner SMs’ capacitor voltage ripple at lower modulation indices. Instead, the circulating current injection of the second harmonics effectively reduces the voltage ripple at higher modulation indices. Thus, maximum reduction in the total capacitance requirement for the entire operating range of modulation index can be achieved by a proper combination of the two solutions. Simulation and experimental results on a laboratory-scaled prototype verify the validity of the proposed solution.