Active Feedback Topology Research Articles

Wideband inductorless transimpedance amplifier using capacitive degeneration and negative capacitance

AbstractThis paper presents a new wideband inductorless CMOS transimpedance amplifier (TIA) for 10Gb/s applications. In this proposed TIA, inverter‐based common‐drain active feedback topology is modified by introducing a cascode transistor to reduce input impedance. Furthermore, capacitive degeneration and negative capacitance techniques are employed by using a single capacitor. Both techniques extend the bandwidth. Mathematical analysis of the proposed TIA has been done using the small signal model to describe bandwidth extension. To verify the theoretical description, the proposed TIA is simulated using TSMC 0.18 μm CMOS technology at 1.8 V power supply with 4.3 mW power consumption. The input photodiode capacitance is 0.25 pF. Simulation results show the transimpedance gain of 51.4 dBΩ and 7.6 GHz bandwidth. The input noise current spectral density is 27 pA/√Hz.

A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers

This paper presents a comparative analysis between two new architectures for RF programmable-gain amplifiers (RFPGAs): voltage-mode RFPGA-V and current-mode RFPGA-I. RFPGA-V utilizes multiple-switch-multiple-amplifier configuration and gain interpolation method to achieve a fine gain step of 0.25-dB over 42-dB gain range for the band of 250 MHz to 2.3 GHz. Meanwhile, RFPGA-I uses a current steering approach to achieve a fine gain step of 0.25-dB over 42-dB gain range for an even wider band of 250 MHz to 3.4 GHz. Since the active feedback topology is used, no off-chip inductor is needed in either RFPGA, especially for the low-frequency band. In addition, both RFPGA-V and RFPGA-I are able to handle maximum 4.4 V peak-to-peak input signal without compromising their high operating bandwidth. Two broadband RF front ends for direct sampling receivers, which include either RFPGA-V or RFPGA-I followed by the same gain buffer and RF filter, have been demonstrated. For the RF front end with RFPGA-V, the measured gain, noise figure, third-order input-referred intercept point (IIP3), and second-order input-referred intercept point (IIP2) in the differential mode are 29.5 dB, 5.2 dB, −10.9 dBm, and 31.4 dBm, respectively. With RFPGA-I, they are 30.5 dB, 3 dB, −10.5 dBm, and 21.1 dBm, respectively. Both RF front ends consume approximated 50 mW and occupy the similar area of 0.32 mm2 in 28-nm CMOS technology.

A 1.4-mW 14-MHz MEMS Oscillator Based on a Differential Adjustable-Bandwidth Transimpedance Amplifier and Piezoelectric Disk Resonator

This paper presents an oscillator based on a fully differential adjustable-bandwidth transimpedance amplifier (TIA) and a piezoelectric micromachined bulk-mode disk resonator. The TIA includes a regulated cascode stage and a common source active feedback topology. The TIA is designed in 65-nm CMOS and consumes 1.4 mA from a 1-V supply. The measured maximum mid-band transimpedance gain is ~80 dB $\boldsymbol {\Omega }$ and the TIA features an adjustable bandwidth of up to 214 MHz, when driving a shunt parasitic capacitance $C_{P}$ of 4 pF. The measured input-referred current noise of the TIA at mid-band (i.e., ~20 kHz–40 MHz) is below 3.7 pA/ $\boldsymbol {\sqrt {\text {Hz}}}$ . The TIA is connected with the disk resonator in [1] , and the oscillator performance in terms of phase noise and frequency stability is reported. The measured phase noise in air and under vacuum, at a 1-kHz offset, is −104 and −116 dBc/Hz, respectively. The close-to-carrier phase noise is also low in air and under vacuum with −40 and −60 dBc/Hz, respectively, at a 10-Hz offset, while the far-from-carrier phase noise reaches −130 dBc/Hz. The measured short-term stability of the MEMS oscillator is of ±0.38 ppm.

0.058 mm 2 13 Gbit/s inductorless analogue equaliser with low‐frequency equalisation compensating 15 dB channel loss

An inductorless 13 Gbit/s analogue equaliser with an additional low-frequency equalisation (LFEQ) to counter the low-frequency channel losses is presented. An active feedback topology for the proposed equaliser together with negative capacitance circuit is used to extend the bandwidth to compensate a 15 dB channel loss at Nyquist. The LFEQ improves the measured data jitter of the conventional equaliser from 0.41 to 0.12 UI, for a pseudorandom binary sequence of 2 31 - 1. The proposed prototype was implemented in 65 nm CMOS, occupying active area of merely 0.058 mm 2 . It exhibits a power efficiency of 1.07 mW/Gitb/s under a supply voltage of 1.2 V and a BER <; 10 -12 .

A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology

A 10-Gb/s low-power analog equalizer for a 10-m coaxial cable has been realized in 0.13-mum CMOS technology. To compensate the cable loss of 20 dB at 5 GHz, this equalizer with an interleaved active feedback topology is proposed without using inductors. Moreover, additional capacitive and resistive source degenerations are incorporated to meet low-frequency losses. This circuit consumes only 14 mW (excluding the output buffer) from a 1.2-V supply with the output swing up to 400 mVpp, and it occupies 0.38 times 0.34 mm2. For 8-, 9-, and 10-Gb/s pseudorandom binary sequences (PRBSs) of 231 - 1, the measured maximum peak-to-peak jitters are 26, 34, and 40 ps, respectively, and the measured bit error rate (BER) is less than 10-12.

GaAs-based high-gain direct-coupled distributed preamplifier using active feedback topology

A single-chip ultra-high gain distributed amplifier (DA) was developed using commercial GaAs PHEMT foundry for 40-Gb/s base band applications. Two seven-section DAs are directly coupled using a lumped dc level-shift circuit. The dc bias level of the second-stage DA can be tuned using the level-shift circuit for optimum gain. The gain of each DA stage has been optimized using a novel active feedback cascode topology, which allows the gain bandwidth product to be maximized while avoiding instability problems. The fabricated single-chip DA with a size of 2.1 mm /spl times/ 2.3 mm showed a high gain of 28 dB, and an average noise figure of 4.6 dB with a 41 GHz bandwidth. The corresponding transimpedance gain was 62 dB/spl Omega/ and the input noise current density was 14.5 pA//spl radic/Hz. The gain bandwidth product (GBWP) is 1030 GHz, which corresponds to the highest performance using GaAs technology for 40 Gb/s applications.