Active Area Width Research Articles

Fabrication and optimization of 1.55-μm InGaAsP/InP high-power semiconductor diode laser**Project supported by the National Natural Science Foundation of China (Nos. 61274046, 61201103) and the National High Technology Research and Development Program of China (No. 2013AA014202).

A comprehensive design optimization of 1.55-μm high power InGaAsP/InP board area lasers is performed aiming at increasing the internal quantum efficiency (ηi) while maintaining the low internal loss (αi) of the device, thereby achieving high power operation. Four different waveguide structures of broad area lasers were fabricated and characterized in depth. Through theoretical analysis and experiment verifications, we show that laser structures with stepped waveguide and thin upper separate confinement layer will result in high ηi and overall slope efficiency. A continuous wave (CW) single side output power of 160 mW was obtained for an uncoated laser with a 50-μm active area width and 1 mm cavity length.

Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes

We investigate in this work an original contact architecture to address 64nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment.Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations.It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography.When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances.At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage VDD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption.

Influence of temperature change on conductive characteristics of titanium oxide memristor

Nano-scaled titanium oxide memristors exhibit unstable conductive characteristics under the same test condition: restricting the possibility to have accurate reading and control of the transient resistance of the device. Moreover, the reliability and stability of memristor-based circuits cannot be guaranteed. Coexistence of dopant drift and tunnel barrier is one of possible origins which causes undesirable instability, and the ambient temperature has a close relationship with dopant drift. However, there have been no detailed researches which may improve the stability of memristors by controlling temperatures. Based on the coexistence of dopant drift and tunnel barrier, the connections between temperature and memristor conductive characteristics are analyzed, and the influences of changes of active area width and initially doped layer width on the critical temperature are studied. Simulations are performed in SPICE and the results are given in this paper. In conclusion, methods are proposed for enhancing the conductive stability of memristors, which include increasing the active area width, decreasing the initially doped layer width, keeping the temperature to be under the critical value, and stability. Our work may provide a basis for manufacturing memristors with stable performance and promoting the practical circuit in applications.

TiN/titanium–aluminum oxynitride/Si as new gate structure for 3D MOS technology

Titanium-aluminum oxynitride (TAON) has been used as high-k gate dielectric for planar MOS devices (capacitors and transistors) and obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation on Si substrates. Thus, planar MOS (Al/TAON/Si) capacitors were characterized by TEM and EDS analyses, and the film formation with thickness of 6.7nm and with Ti, Al, O and N into the TAON dielectric bulk is confirmed. However, for future 3D device technology application, these films have been not investigated. So, 3D MOS capacitors with Al/TAON/Si (as control sample) and TiN/TAON/Si gate structures for 3D technology were fabricated. Al/TAON and TiN/TAON layers on 3D gate region must present conformal coverage, which is a mandatory requirement for 3D transistors, such as FinFET. To characterize the TAON conformal coverage for this technology, the gate structure formed by Al/TAON/Si for FinFETs were fabricated and the ''Fin'' structures were obtained using a Focused Ion Beam (FIB) system to become thinner the width of active area to get the ''Fin'' structure. C-V curves of these structures were performed at 1MHz, and the three C-V curve regions (accumulation, depletion and inversion) are well defined for all capacitors, indicating that the conformal coverage on the 3D and FinFET gate regions can be occurred. Furthermore, these results indicated that TiN/TAON layers can be used as a new alternative for 3D MOS structures.

Active Area Width and Topography Effects on Sub 45nm Poly Gate CD

Gate critical dimension (CD) is an important parameter in determining the CMOS device performance. During the process of aggressive feature size shrinking in 45nm node and beyond, aside from the recognized topographical impact on the wafer-to-wafer CD variation, the active area (AA) width has to be taken into consideration for the thorough analysis and the rigid control of within-wafer gate CD variation. Roughly 5%~8% within-wafer CD difference was observed on six gate structures (the same defined gate with different AA widths) right after the gate etch. Both topography wafer and blank wafer (deposited merely with gate oxide plus poly-Si) were utilized to identify the potential key contributors to such within-wafer CD variation. Results demonstrate that the shallow trench isolation (STI) step height, one of notorious topography factors, heavily relies on the local AA width. This leads to the instability of poly-Si film thickness, therefore resulting in the inconsistency of gate bottom profile. Despite, the optical proximity correction (OPC) based on the post-gate etch CD could be utilized to assuage the AA width related CD difference to some extent, the dependence of step height on AA width from the synergetic action of CMP and WET process should be solved for the fundamental solution to such within-wafer gate CD variation.

Model for series resistance photovoltaic performance of large-scale dye-sensitized solar cells

The dependence of photocurrent and photovoltage of dye-sensitized solar cell on the incident light intensity were investigated based on the electron continuity diffusion equation. For the first time a model was presented for power loss of series resistance in dye-sensitized solar cell, and were simulated the influence of the active-area width of nanoporous film, the effect of special contact resistance on the photo-electric conversion efficiency, as well as the silver impedance in lager-scale solar cells with active area greater than 1 cm2 under different illuminations. It was found that the efficiency strongly depends on the width of active area and the silver impedance under strong illumination, nevertheless, this dependence is not obvious under poor illumination.

Shallow trench isolation dimensions effects on leakage current and doping concentration of advanced p–n junction diodes

This paper describes the impact of active area and shallow trench isolation (STI) width on the junction leakage current and doping concentration. A higher junction leakage current is found for a narrower active area and STI width. This is mainly due to a higher compressive stress. This compressive stress also affects the doping concentration near the junction. A higher compressive stress when reduce active area width causes a higher doping concentration while a higher compressive stress when reduce STI width results in a lower doping concentration.

Further study on selective TiSi 2 deposition by CVD

Selective chemical vapor deposition (CVD) of TiSi 2 has been obtained from TiCl 4/DCS/H 2 chemistry using an industrial integrated cluster reactor. First, some fundamental aspects were studied in order to better understand the process. Prior to deposition, an incubation time exists which increases with decreasing deposition temperature. For temperatures between 650 and 780°C, the growth rate is limited by the TiCl 4 flow. This CVD technique was then used on device wafers and we obtained low sheet resistances of down to 0.2 μm in poly linewidth and 0.12 μm in active area width. Leakage currents on diode structures are shown to be essentially dependent on residual implantation defects, and thus, on implantation conditions. To conclude, CVD TiSi 2 has been validated on a microprocessor circuit fabricated in a 0.35 μm CMOS process and the yield obtained is comparable to that obtained using the standard salicide technique with fewer technological steps.

Some graphical methods for maintenance planning : Bo. Berman. Proc. IEEE Reliab. Maintainab. Symp. Philadelphia, 18–20 Jan. 1977. p. 467

We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment.Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations.It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography.When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances.At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage VDD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption.