Active Area Width and Topography Effects on Sub 45nm Poly Gate CD

Abstract

Gate critical dimension (CD) is an important parameter in determining the CMOS device performance. During the process of aggressive feature size shrinking in 45nm node and beyond, aside from the recognized topographical impact on the wafer-to-wafer CD variation, the active area (AA) width has to be taken into consideration for the thorough analysis and the rigid control of within-wafer gate CD variation. Roughly 5%~8% within-wafer CD difference was observed on six gate structures (the same defined gate with different AA widths) right after the gate etch. Both topography wafer and blank wafer (deposited merely with gate oxide plus poly-Si) were utilized to identify the potential key contributors to such within-wafer CD variation. Results demonstrate that the shallow trench isolation (STI) step height, one of notorious topography factors, heavily relies on the local AA width. This leads to the instability of poly-Si film thickness, therefore resulting in the inconsistency of gate bottom profile. Despite, the optical proximity correction (OPC) based on the post-gate etch CD could be utilized to assuage the AA width related CD difference to some extent, the dependence of step height on AA width from the synergetic action of CMP and WET process should be solved for the fundamental solution to such within-wafer gate CD variation.