Active Area Dimensions Research Articles

Study on Bottom Distributed Bragg Reflector Radius and Electric Aperture Radius on Performance Characteristics of GaN-Based Vertical-Cavity Surface-Emitting Laser.

This article presents the results of a numerical analysis of a nitride-based vertical-cavity surface-emitting laser (VCSEL). The analyzed laser features an upper mirror composed of a monolithic high-contrast grating (MHCG) and a dielectric bottom mirror made of SiO2 and Ta2O5 materials. The emitter was designed for light emission at a wavelength of 403 nm. We analyze the influence of the size of the dielectric bottom mirrors on the operation of the laser, including its power-current-voltage (LIV) characteristics. We also study the effect of changing the electrical aperture radius (active area dimensions). We demonstrate that the appropriate selection of these two parameters enables the temperature inside the laser to be reduced, lowering the laser threshold current and increasing its optical power output significantly.

Area-dependent performance variation of ultrasonic spray-coated organic solar cells

Here, a comparative study has been performed to understand the scalability of as developed ultrasonic spray deposition process for large-area organic solar cell fabrication. It was observed that the performance of the devices reduces with increasing active area dimensions. The short circuit current density and power conversion efficiency got decreased by more than 70% on increasing the device area from 0.04 to 1.5 cm2. In the case of small-area devices, the low electrical resistance owing to fewer droplet boundaries and negligible pinholes of the spray-coated film leads to better device performance. Whereas, upon scaling up the device area, the non-uniformity of the spray-coated film starts dominating and is found to be responsible for the reduction in overall device performance. The non-homogeneous film morphology in the case of larger-area devices greatly affects the charge generation, as it decreased from 4.77 × 1021 to 1.92 × 1021 cm−3 s−1 for large-area devices compared to small-area ones. The results suggest that the spray-deposited films greatly suffer from the limitation of droplet boundaries and pin-holes, which need to be addressed further with post-deposition treatments, in order to fabricate commercially viable large-area devices.

Magnetopiezofiber

The results of the magnetoelectric effect study in the magnetopiezofiber are presented. Magnetopiezofiber consists of mechanically coupled piezoelectric (one layer of lead zirconate titanate) and magnetostrictive (two metglass layers) fibers. The layers were joined together by epoxy under pressure and heating. The sample active area dimensions were 28x7x0,34 mm. The study of the magnetoelectric effect was carried out in the frequency range from 0 to 150 kHz and external magnetic field range from 0 to 100 Oe. Maximum value of the ME voltage coefficient αE = 62,75 V/cm-Oe was measured on the electromechanical resonance frequency f = 61 kHz with an external magnetic field of 4,5 Oe. Obtained results indicate the prospects of the proposed design in magnetoelectric devices application.

On the use of a localized STRASS technique to obtain highly tensile strained Si regions in advanced FDSOI CMOS devices

AbstractStrain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile channels. We present an alternative technique to blanket sSOI substrates. The efficiency of the “Strained Silicon by Top Recrystallization of Amorphized SiGe on SOI” technique has been previously successfully demonstrated on blanket SOI (+ 1.6 GPa tensile strain achieved). Here we demonstrate a simple and efficient STRASS module integration in an advanced FDSOI route (14 nm design rules) which allows to cointegrate tensile Si for nFETs and unchanged pFETs.After pFETs have been protected (SiN), the STRASS technique has been used in the SOI nFET patterns. This process requires SiGe selective epitaxy, buried amorphization by ion implantation, recrystallization and SiGe removal. Raman spectroscopy is used to characterize the stress in Si areas with respect to process conditions (implantation, active area dimensions). Moreover, the mechanisms of SiGe relaxation will be discussed as function of device dimensions and SiGe layer properties (thickness, Ge content). We demonstrate the successful integration of localized STRASS module: tensile Si patterns (for nFETs) with a level of stress of + 1.6 GPa, cointegrated with unmodified pFETs. (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Impedance spectroscopy on stretchable microelectrode arrays

We are reporting on the fabrication and electrical characterization of stretchable polydimethylsiloxane (PDMS) based microelectrode arrays for recording of neuronal action potentials. Electrodes are immersed in phosphate buffered saline solution. Their electrical impedance spectra are recorded as a function of uniaxial macroscopic strain applied using a custom built automated stretcher. We propose a model to account for the physical phenomena responsible for electrical conduction in the bulk electrode and at the metal–electrolyte interface. Electrodes with active area dimensions of 100×140 μm2 maintain an impedance of approximately 1 MΩ at 1 kHz when cycled to 20% strain.

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes