Achieve Fault Tolerance Research Articles

FDR: fault detection and recovery scheme for wireless sensor networks using virtual grid

Due to autonomous operation and constrained resources, nodes of a wireless sensor network are susceptible to failures. Due to multiple node failures, network topology may change or partition into many disconnected segments causing data/query path breakage. Early detection and recovery of faults is desirable in most scenarios. Also, due to limited battery life of a node, the solution must consume minimum possible energy for prolonged network operation. Hence in this paper, we propose a Fault Detection and Recovery scheme which is an energy efficient fault detection and recovery strategy that achieves minimum data loss by efficiently replacing faulty node on the present route or by finding full or partial alternate paths. Topology is managed by constructing a virtual grid over the entire network which helps in managing dynamically changing network topology easily and makes failure detection and recovery effective. It also helps to create energy efficient path between a source and a sink by finding shortest possible path. Further, nodes’ cooperation is exploited to create certain zones on the data/query path which provides alternate nodes or possible alternate paths if required on some node failures. Thus, scheme achieves fault tolerance and at the same time achieves energy efficiency by always selecting shortest path for data delivery between source and sink. Analytical and simulation study reveals the significant improvement in terms of fault detection and energy conservation over existing similar schemes.

Area Reduction in Redundancy Module for an ECC Based Fault Tolerance in Digital Filters

Due to the wide usage of digital filters in communication systems, reliability and area has to be considered and deficiency tolerant channel usage are required. Throughout the decades, there are number of techniques that have been proposed to achieve fault tolerance. As the number of parallel filters are increasing in any digital device, the redundancy module should also be small in size. In this paper, a simple technique of constant multiplication reduction method is introduced in the Error Correction Codes (ECC) based parallel filters in order to reduce the size of the redundant module. Main agenda is to reduce the size of the redundant module by not affecting the functionalityof the system. The proposed scheme is coded in HDL and simulation results are obtained by using Xilinx 12.1i. The presented result shows that the slices can be reduced and hence the size. As a result of reduction in size, the optimization of area can also be concluded. Index Terms—Fault tolerance, ECC, Xilinx, Slices, LUT, Digital filters.

Adaptive coordinated leader–follower control of autonomous over-actuated electric vehicles

In this paper, the leader–follower formation control problem of autonomous over-actuated electric vehicles on a highway is studied. As the autonomous over-actuated electric vehicles have the characteristics of non-linearities, external disturbances and strong coupling, a novel coordinated three-level control system is constructed to supervise the longitudinal and lateral motions of autonomous electric vehicles. Firstly, an adaptive terminal sliding high-level control algorithm is designed to compute a vector of total forces and torque of vehicles, and the stability of the high-level control system is proven via Lyapunov analysis where uniform ultimate boundedness of the closed-loop signals is guaranteed. Then, a pseudo-inverse control allocation algorithm, which can achieve fault tolerance and reconfiguration of the redundant tyre actuation system, is presented to generate the desired longitudinal and lateral tyre forces. Then, a separate low-level controller consisting of an inverse tyre model and two inner loops for each wheel is designed to achieve its desired forces. Finally, simulation results demonstrate that the proposed control system not only enhance the tracking performance, but also improve the stability and riding comfort of autonomous over-actuated electric vehicles in a platoon.

A Novel Time Synchronization Method for Dynamic Reconfigurable Bus

UM-BUS is a novel dynamically reconfigurable high-speed serial bus for embedded systems. It can achieve fault tolerance by detecting the channel status in real time and reconfigure dynamically at run-time. The bus supports direct interconnections between up to eight master nodes and multiple slave nodes. In order to solve the time synchronization problem among master nodes, this paper proposes a novel time synchronization method, which can meet the requirement of time precision in UM-BUS. In this proposed method, time is firstly broadcasted through time broadcast packets. Then, the transmission delay and time deviations via three handshakes during link self-checking and channel detection can be worked out referring to the IEEE 1588 protocol. Thereby, each node calibrates its own time according to the broadcasted time. The proposed method has been proved to meet the requirement of real-time time synchronization. The experimental results show that the synchronous precision can achieve a bias less than 20 ns.

Design and Development of Reliable Energy based Efficient Protocol for Improving Fault Tolerance in MANET

In recent years, mobile unexpected networks offers new challenges and goals in fault tolerant computing space. Mobile nodes will communicate while not a hard and fast infrastructure. A study of analysis work on fault tolerance reveals that, fault tolerance is achieved with or while not information concerning neighbors. High quality of nodes ends up in path failures, that degrades the performance of networks and affects the whole network property. A theme termed as Reliable Stable Path Routing (RSPR) is planned for achieving fault tolerance level and most packet delivery rate. To balance the fault tolerance level and cargo equalisation, multipath routing with stability metric is planned. The planned approach improves the network life and network performance. supported the less packet loss rate, additional residual energy and transmission chance, reliable forwarding nodes square measure chosen. Packets square measure routed supported the placement of reliable nodes. a replacement channel is discovered for economical packet delivery with stability. within the end of the planned approach, location of the destination node is updated to all or any the reliable forwarding nodes. This update improves the fault tolerance, packet delivery chance and avoids the network load. Simulation results show that the planned protocol RSPR achieves higher performance in comparison with the present schemes LAER and CDN.

A Network Coding Based Energy Efficient Data Backup in Survivability-Heterogeneous Sensor Networks

Sensor nodes deployed outdoors are subject to environmental detriments and often need to cache data for an extended period of time. This paper introduces sensor nodes which are robust to environmental damages, and proposes to utilize Network Coding to back up data in the robust sensors for future data retrieval in an energy efficient way. Our goal is to help regular sensors select robust sensors to back up their data with low energy consumption, such that when needed, all the data can be retrieved by querying only a subset of robust sensors. We formally formulate this backup problem, theoretically prove its NP-Completeness, discover two novel theoretical guidelines for problem solving, and propose two algorithms accordingly to tackle this NP-C problem. The guidelines are based on random linear network coding and provide lower bounds of the number of robust sensors that each regular sensor should choose for data backup, such that the required fault tolerance is provided. A centralized algorithm and a distributed algorithm are developed based on the guidelines such that regular sensors can back up their data efficiently. Both analysis and simulation show our algorithms are effective in achieving fault tolerance, low energy consumption, and high retrieval efficiency.

Optimal Design of Hybrid Redundant Systems With Delayed Failure-Driven Standby Mode Transfer

Standby redundancy is a design technique that has been widely adopted to enhance system reliability and achieve fault tolerance in many critical applications. In this paper, we consider a 1-out-of- N: G hybrid standby redundant system with unrepairable elements being subject to delayed failure-driven standby mode transfers. Specifically, in the considered system, all the standby elements are initially in a warm standby mode (WSM) but can be transferred to a hot standby mode (HSM) so as to be ready to replace the online operating element when it fails. The WSM to HSM transfer is performed with a fixed time delay after no element resides in HSM either due to the element failure or because the element leaves the HSM to replace the failed online element for operation. A new iterative numerical algorithm is first proposed for evaluating reliability and expected mission cost (relevant to elements’ standby expense, operation expense, as well as mode transfer expense) of the considered hybrid standby system. The algorithm has no restriction on element time-to-failure distribution types. Based on the proposed evaluation algorithm, we further formulate and solve a new optimization problem that finds the optimal delay and optimal sequence of standby elements with the objective to minimize expected mission cost while satisfying a certain level of mission reliability constraint. Examples are presented to demonstrate applications of the proposed methodology.

Reliable [formula omitted] control for uncertain nonlinear discrete-time systems subject to multiple intermittent faults in sensors and/or actuators

This study focuses on passive fault-tolerant control for a class of uncertain nonlinear discrete-time systems subject to multiple intermittent faults. The considered intermittent faults are assumed to be additive ones in sensors and/or actuators. To achieve fault-tolerant control, a dynamic output-feedback controller is designed such that the closed-loop system remains stable and satisfies acceptable performance, even when there are parameter uncertainties, nonlinearities of specific type, and multiple additive intermittent sensor and/or actuator faults. The linear matrix inequality method is employed to obtain sufficient conditions for achieving fault tolerance and ensuring the prescribed H∞ performance index. Finally, the effectiveness of the proposed method is demonstrated by simulation examples.

Movement-Based Checkpointing and Message Logging for Recovery in MANETs

Mobile ad hoc networks (MANETs) are increasingly being employed for expanding the computing capabilities of existing cellular mobile systems and in the implementation of mobile computing grids. However, MANETs are susceptible to various transient as well as permanent failures and a fault tolerance technique is crucial in order to effectively utilize the constituent nodes as viable compute resources. Checkpointing and message logging based rollback recovery is a well established approach to provide fault tolerance in static and cellular mobile distributed systems; yet its use for achieving fault tolerance in MANETs is comparatively less explored. The existing recovery algorithms cannot be applied directly to MANETs due to their insufficiency in handling challenges like absence of static infrastructure, frequent node movement, constrained wireless bandwidth and limited stable storage. In this paper, we propose a checkpointing based rollback recovery protocol for clustered MANETs that determines the checkpointing frequency of a mobile node based on its mobility; thereby avoiding unnecessary checkpoints. The protocol uses a popular graph theoretic construct called connected dominating set to lower the communication overhead due to the recovery procedure. The findings of our scheme have been substantiated by the complexity analysis and simulation under varying network conditions.

Fault Tolerant Parallel Filters Based on Error Correction Codes

Digital filters are widely used in signal processing and communication systems. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that exploit the filters' structure and properties to achieve fault tolerance have been proposed. As technology scales, it enables more complex systems that incorporate many filters. In those complex systems, it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC. This new scheme allows more efficient protection when the number of parallel filters is large. The technique is evaluated using a case study of parallel finite impulse response filters showing the effectiveness in terms of protection and implementation cost.

Fault-Tolerant Control of Discrete-Event Systems with Lower-Bound Specifications

Abstract: Fault-tolerant control addresses the control of dynamical systems such that they remain functional after the occurrence of a fault. To allow the controller to compensate for a fault, the system must exhibit certain redundancies. Alternatively, one may relax performance requirements for the closedloop behaviour after the occurrence of a fault. To achieve fault tolerance for a hierarchical control architecture, a combination of both options appears to be advisable: on each individual level of the hierarchy, the controller may compensate the fault as far as possible, and then pass on responsibility to the next upper level. This approach, when further elaborated for discrete-event systems represented by formal languages, turns out to impose a hard lower-bound inclusion specification on the closed-loop behaviour. The present paper discusses the corresponding synthesis problem and presents a solution.

Bayesian Network Based Fault Tolerance in Distributed Sensor Networks

A Distributed Sensor Network (DSN) consists of a set of sensors that are interconnected by a communication network. DSN is capable of acquiring and processing signals, communicating, and performing simple computational tasks. Such sensors can detect and collect data concerning any sign of node failure, earthquakes, floods and even a terrorist attack. Energy efficiency and fault-tolerance network control are the most important issues in the development of DSNs. In this work, two methods of fault tolerance are proposed: fault detection and recovery to achieve fault tolerance using Bayesian Networks (BNs). Bayesian Network is used to aid reasoning and decision making under uncertainty. The main objective of this work is to provide fault tolerance mechanism which is energy efficient and responsive to network using BNs. It is also used to detect energy depletion of node, link failure between nodes, and packet error in DSN. The proposed model is used to detect faults at node, sink and network level faults ( link failure and packet error). The proposed fault recovery model is used to achieve fault tolerance by adjusting the network of the randomly deployed sensor nodes based on of its probabilities. Finally, the performance parameters for the proposed scheme are evaluated.

A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips

Nowadays, three dimensional Network-On-Chips (NOCs) have emerged as most efficient and scalable communication structures for complex and high performance System-on-Chips (SOCs). These structures are so susceptible to manufacturing and runtime faults. Thus fault tolerant routing is essential to increase reliability and performance of NOC-based SOCs. In this paper, we propose FT-DyXYZ, an adaptive fault tolerant routing to tolerate permanent faulty links in 3D mesh based NOCs that uses proximity congestion information to balance traffic. Our routing achieves fault tolerance without using routing tables, redundancy or global information of paths and faults. To evaluate performance of our routing, we compared it with fault tolerant planar-adaptive routing in terms of average packet latency, throughput and reliability. Simulation results demonstrate significant improvement of saturation injection rate, average throughput and reliability of our routing under synthetic traffic patterns.

Fault tolerant distributed real time computer systems for I&C of prototype fast breeder reactor

Prototype fast breeder reactor (PFBR) is in the advanced stage of construction at Kalpakkam, India. Three-tier architecture is adopted for instrumentation & control (I&C) of PFBR wherein bottom tier consists of real time computer (RTC) systems, middle tier consists of process computers and top tier constitutes of display stations. These RTC systems are geographically distributed and networked together with process computers and display stations. Hot standby architecture comprising of dual redundant RTC systems with switch over logic system is deployed in order to achieve fault tolerance. Fault tolerant dual redundant network connectivity is provided in each RTC system and TCP/IP protocol is selected for network communication. In order to assess the performance of distributed RTC systems, scaled down model was developed with 9 representative systems and nearly 15% of I&C signals of PFBR were connected and monitored. Functional and performance testing were carried out for each RTC system and the fault tolerant characteristics were studied by creating various faults into the system and observed the performance. Various quality of service parameters like connection establishment delay, priority parameter, transit delay, throughput, residual error ratio, etc., are critically studied for the network.

A Comparative Study of Pre-Copy based Live Virtual Machine Migration Techniques

Virtual Machine(VM) migration is a powerful management technique that gives data center users the ability to adapt the placement of VMs in order to better satisfy performance objectives, improve resource utilization and communication locality, load balancing, mitigate performance hotspots, achieve fault tolerance, reduce energy consumption, and facilitate system maintenance activities. Live migration defines movement of VMs form one physical host to another without disrupting the client or application. One of the objectives of live migration is that it should have minimum migration time as well as downtime so that applications running on VM are suspended for negligible time. In this paper we focus on various pre-copy based live virtual machine migration techniques and compare them based on key performance metrics like downtime, total migration time, total no of bytes transferred, etc. Keywords: Virtualization; Virtual Machine; Live Migration; Downtime; Total Migration Time; Pre Copy

Imperfect construction of microclusters

Microclusters are the basic building blocks used to construct cluster states capable of supporting fault-tolerant quantum computation. In this paper, we explore the consequences of errors on microcluster construction using two error models. To quantify the effect of the errors we calculate the fidelity of the constructed microclusters and the fidelity with which two such microclusters can be fused together. Such simulations are vital for gauging the capability of an experimental system to achieve fault tolerance.

A Quantitative Analysis of a Novel SEU-Resistant SHA-2 and HMAC Architecture for Space Missions Security

The increasing demand for more secure operation of space missions has led to emergence of cryptographic mechanisms aboard spacecrafts. However, cryptographic applications are extremely sensitive to bit-flips caused by radiation-induced single event upsets (SEUs). A traditional approach to mitigate SEUs in space applications has been the triple modular redundancy (TMR). However, such technique incurs large overheads in implementation area and power. An efficient approach to achieve fault tolerance in the secure hash standard (SHS) and in the keyed-hash message authentication code (HMAC) is introduced. When compared with TMR the proposed scheme not only achieves higher resistance against SEUs, but it also reduces implementation area requirements and power consumption. Results obtained through field-programmable gate array (FPGA) implementation show that HMAC/SHA-512 (secure hash algorithm) utilizes, on average, 53% less area and less power compared with the traditional TMR technique. Furthermore, the memory and registers of the HMAC/SHA-512 module are approximately 171 and 491 times more resistant against SEUs than TMR. This research is crucial for enabling the efficient employment of security mechanisms onboard space systems.

A Survey on Localization and Covering Techniques in Wireless Sensor Networks

Sensor Network (WSN) has gained popularity in diverse application fields owing to the inexpensive sensor nodes also called as motes. These sensor nodes are either deployed randomly or placed manually depending on the type of applications. The services of WSN are tremendously being used in application areas such as disaster relief, search and rescue, target tracking, battlefield and many more. Due to the application of WSN in such environments, it is not possible to manually deploy sensor nodes and therefore, the nodes are randomly deployed in the area of interest. Due to the random placement of the sensor nodes, it becomes essential to determine the location of the nodes in order to facilitate communication between nodes as well as Base Station (BS). Further, in case of random node deployment, the usual practice is to deploy a very large number of nodes (more than that of the requirement) in the area of interest. This is done in order to achieve fault tolerance, thus opening a large number of research directions to determine the optimal number of nodes participating in WSN 'covering' problem. This paper deals with an insight on the various localization and coverage techniques used in WSN. Further this paper tries to establish the interdependence between the localization and covering techniques.

Efficient reconfiguration algorithms for communication-aware three-dimensional processor arrays

Abstract Homogeneous processor arrays are emerging in tera-scale computation and effective fault tolerance techniques are essential to improving the reliability of such complex integrated circuits. We study the degradable processor arrays to achieve fault tolerance by employing reconfiguration. Three bypass schemes and three rerouting schemes are proposed to reconfigure three-dimensional processor arrays with defective processors to achieve target arrays without faults. A heuristic algorithm is proposed to construct a target array on the selected rows and columns. It is also proved that the proposed greedy plane rerouting algorithm (GPR) produces maximum target array. In addition, the problem of constructing the communication efficient array is considered in this paper. An algorithm is proposed to refine the communication among processors within the target array constructed by GPR. Experimental study shows that the proposed algorithm GPR produces target arrays with higher harvest and lower degradation on the host arrays with fault density no more than 5%. In addition, the communication performance is significantly optimized by reducing the number of long interconnects, and the average improvement is about 34% for all cases considered in this paper.

Distributed Control of a Fault-Tolerant Modular Multilevel Inverter for Direct-Drive Wind Turbine Grid Interfacing

Modular generator and converter topologies are being pursued for large offshore wind turbines to achieve fault tolerance and high reliability. A centralized controller presents a single critical point of failure which has prevented a truly modular and fault-tolerant system from being obtained. This study analyzes the inverter circuit control requirements during normal operation and grid fault ride-through and proposes a distributed controller design to allow inverter modules to operate independently of each other. All the modules independently estimate the grid voltage magnitude and position, and the modules are synchronized together over a controller area network (CAN) bus. The CAN bus is also used to interleave the pulsewidth modulation switching of the modules and synchronize the analog to digital converter (ADC) sampling. The controller structure and algorithms are tested by laboratory experiments with respect to normal operation, initial synchronization to the grid, module fault tolerance, and grid fault ride-through.