Overlay Measurement Accuracy Research Articles

Calibration method of overlay measurement error caused by asymmetric mark.

With the process nodes extending to sub-10-nm in advanced semiconductor manufacturing, the overlay requirements keep progressively scaling down, which makes it very important to measure overlay precisely for monitoring on-product performance. The overlay mark being asymmetrical when generated via the lithography process, this asymmetry will be slightly variated even in the same process or same lot, and it will bring overlay measurement error. In general, the wafer alignment data are used for correcting this overlay measurement error, utilizing its wavelengths and polarizations dependence. However, there is a residual error that cannot be removed because the structures of the wafer alignment mark and overlay mark are different and are affected by the process differently. In this paper, a new method is proposed for calibrating the overlay measurement error introduced by the asymmetric mark, which is based on the relationship between measurement data of the overlay mark and the single layer mark. The validity is verified by simulation with different types of asymmetric mark. It is very useful for improving overlay measurement accuracy and for understanding how the overlay measurement error is affected by the asymmetric mark.

Enhancement of printing overlay accuracy by reducing the effects of mark deformations

The roll-based high-speed printing process has the two major advantages of high productivity and a simple process over the conventional electronic device manufacturing process. There have been several attempts to commercially apply the roll-based high-speed printing process to various electronic devices. While such attempts have sought to improve the performance of electronic devices, these devices require multi-layered structures to be printed with high overlay accuracy between each layer. Printed patterns always appear to be deformed compared to the designs on the master plate because the printing process is solution based. Given variations in ink transfer volume, the accuracy of the overlay measurement can be degraded by mark deformations. This means that these deformations caused by the printing mechanism should be taken into account. In this paper, we provide the details from a simulation study and experiment carried out using gravure offset printing to investigate the effects of mark deformations on overlay measurement accuracy. We analyzed and optimized the pattern registration algorithms and the type of overlay marks in order to improve the measurement accuracy of the positions of the printed patterns. As a result, the repeatability measuring the positions of the printed patterns can be reduced to 1.0μm and 2.0μm in the CD and MD directions in the gravure offset printing process, respectively.

Optimization of Sample Plan for Overlay and Alignment Accuracy Improvement

The overlay control requirement for a sub-0.15 µm design rule device is nominally less than 40 nm. To meet this demand, every factor known to affect the overlay budget should be analyzed in detail and corrected as much as possible. One of the major causes degrading the overlay budget is the nonoptimized wafer sample plan. Compensated but undercorrected overlay errors fitted as linear terms can be amplified in case of using improper sample plan (e.g., an asymmetric plan). In this study, we investigated the sample plan dependency of global alignment repeatability and overlay measurement accuracy. The achievement of better alignment repeatability is critical for improving not only in-wafer overlay but wafer-to-wafer overlay control. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected for global alignment use. Several sample plans which are limited to the symmetric group (i.e., translation, inversion, rotation and symmetric), are tested. The criteria for selecting the optimum sample plan were the residuals and linear-term reproducibility, both of which are significantly affected by raw data noise. Raw data variations include stage positioning errors and process-induced alignment signal abnormality. From among the candidates, we determined an optimal sample plan which leaves the least residuals and exhibits repeatability as good as that in full chip measurement. Similar results could be obtained for an overlay sample plan.

Accuracy of overlay measurements: tool and mark asymmetry effects

Definitions of centerline and centerline overlay (O/L) are built on the implicit assumptions of certain symmetries. Verification of these symmetries, and the use of redundancies built into the design of O/L measurement marks, can estimate the relative accuracy of O/L measurements, even in the absence of certified reference materials (standards). Verification carried out as of paired comparison is shown to be very effective; in addition, it constitutes the basis for data culling. Several sources of O/L measurement inaccuracy, associated with O/L measurement tools and with O/L measurement marks, are pointed out and some are illustrated using modeling. A simple measure of tool-related inaccuracy, tool-induced shift (TIS), is proposed and utilized as a performance estimate of O/L measurement tools relative to accuracy. Inaccuracies of O/L measurements, caused by O/L measurement tools and marks, on the order of 100 nm, are observed and their causes identified. Examples are given of significant improvements in accuracy. A roadmap toward accurate O/L measurement is outlined. This approach is also applicable to alignment systems.