Accumulation-mode MOSFET Research Articles

A novel 4H‐SiC accumulation mode MOSFET with ultra‐low specific on‐resistance and improved reverse recovery capability

AbstractA novel 1440‐V 4H‐SiC accumulation mode MOSFET (ACCUFET) with ultra‐low specific on‐resistance and improved reverse recovery performance is proposed in this article. As for the proposed SiC ACCUFET, the channel region can be completely depleted by the P‐type heavily doped polysilicon gate to build an electron barrier and realize a normally‐off device. And a Schottky barrier diode (SBD) is integrated below the trench gates on both sides, which brings the feasibility of realizing reverse conduction function of the proposed ACCUFET. Also, the p‐shield regions under the Schottky contact metal provide a good electric field shielding effect for the gate oxide. Compared with the conventional SiC trench MOSFET, the numerical simulation results show that the specific on‐resistance (Ron,sp) of the proposed ACCUFET is reduced by more than 64%. The high‐frequency figures‐of‐merit HFOM [Ron,sp × Cgd] and HFOM [Ron,sp × Qgd] of the proposed device are improved by 53.19% and 58.74%, respectively. The reverse recovery time (trr), and reverse recovery charge (Qrr) are reduced by 23.28% and 82.73%, respectively. In addition, the results also indicate that the proposed device has a better latch‐up immunity compared with the conventional SiC trench MOSFET. The excellent device performance and the simple manufacturing process provide a good prospect for the application of the proposed device.

Extraction of non-quasi-static model parameters for cylindrical gate-stacked junction-less accumulation mode MOSFET and its implementation as RF filters for circuit applications

Extraction of non-quasi-static model parameters for cylindrical gate-stacked junction-less accumulation mode MOSFET and its implementation as RF filters for circuit applications

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

This article analyses the effect of ion implantation on electrical and circuit-level characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) MOSFET. Ion implantation and subsequent annealing create a Gaussian type doping profile inside the channel. A detailed study of electrical characteristics such as: drain current, threshold voltage, Ion/Ioff, transconductance (gm), output conductance (gd), capacitances (Cgs, Cgd, Cgg), unit gain frequency (fT), transit time (τ), transconductance frequency product (TFP) and gain bandwidth (GBW) product have been performed. Further, an inverter has been designed with a complimentary p-MOSFET and a lookup table-based Verilog-A model has been generated for the same. Various dc and transient parameters such as noise margin, rise time, fall time propagation delay, voltage overshoot, average current, and power dispassion have been analyzed in detail. Henceforth, a 6 T SRAM cell has been implemented with ion-implanted stacked oxide CG-JAM MOSFET and read margin, write margin, access time and N-curve analysis have been performed. Various figures of merits (FOMs) have also been studied for the device at the circuit level. All the device simulations have been performed using a 3-D TCAD tool from COGENDA. Verilog-A model-based circuit simulations have been done in the Cadence-Virtuoso platform.

Total ionizing dose effects in junctionless accumulation mode MOSFET

In this paper, an extensive investigation of low-frequency (1/f) noise and total ionizing dose–response of junctionless accumulation mode double-gate (JAM DG) MOSFET is presented. Current–voltage (Id–Vg) characteristics and low-frequency noise of JAM DG MOSFET are simulated at different ionized doses and compared to different gate oxide thickness and different channel doping concentrations. A significant amount of irradiation-induced threshold voltage shift and increase in low-frequency noise is observed for different gate oxide thickness and channel doping concentration. Moreover, the irradiation-induced border trap densities are also obtained at different doses. The gamma radiation model of Sentaurus TCAD is used to get the required results.

Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry

As short-channel effects (SCEs) are a major issue in the nanoscale regime, investigation of the subthreshold behaviour of nanometer-scale devices is critical. Here, we have developed an analytical model for a cylindrical gate junctionless accumulation-mode MOSFET (Cyl-JLAM MOSFET) to analyse its behaviour in the subthreshold region. The two-dimensional Poisson equation is solved to develop the analytical model by approximating the potential profile along the channel to be parabolic. We have formulated the expression for potential at the centre and electric field along the channel from the developed model. The key performance factors of SCEs including threshold voltage (VTH) roll-off, drain-induced barrier lowering and subthreshold slope are explored with respect to the geometry of the device parameters, i.e. body thickness of the cylindrical silicon pillar, length of the channel and thickness of the oxide layer. The results of our model are in good agreement with numerical simulations. The TCAD ATLAS 3D device simulator accounts for all the physical models required during the simulation. In this paper, the simple and distinctly formulated analytical model supports the application of the Cyl-JLAM MOSFET in integrated circuit design and optimization.

Investigation of Single Event Transient Effects in Junctionless Accumulation Mode MOSFET

The Junctionless Accumulation Mode Double Gate MOSFET (JAM DG MOSFET) is a promising novel architecture for future nano-scaled devices because of its outstanding electrical characteristics, e.g., lower subthreshold swing, lower drain induced barrier lowering, i.e., lower short channel effects and higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio. In this paper, a comprehensive analysis of the effects of single-event transient on JAM DG MOSFET has been performed using the sentaurus TCAD simulator. The result shows that the transient drain current peak obtained after the heavy-ion strike for JAM DG MOSFET is small at lower value linear energy transfer (LET) and high for the larger value of LET. Collected charge at different LET values has also been investigated. Moreover, the sensitive region of the device, e.g., source to channel junction, channel, and channel to drain junction has been studied. It has been found that the drain to channel junction is more sensitive to the linear energy than the channel and source to channel junction. The electrical characteristics have also been compared with JL DG MOSFET.

A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes

This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate nanowire junctionless accumulation mode MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device.

2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET

This paper reports a physics-based analytical model for the cylindrical-gate (CG) asymmetric halo doped graded-channel (GC) dual-material (DM) junctionless-accumulation-mode (JAM) MOSFETs by incorporating both the effects of gate material engineering and channel engineering on the device characteristics. Poisson’s equation has been solved using the superposition technique with appropriate boundary conditions. The minimum central potential concept has been used to derive the threshold voltage model. The drain and gate currents have been modeled by including the effects of gate induced drain leakage (GIDL) and gate leakage currents, respectively. The performance parameters of the proposed CG-GCDM JAM MOSFETs have been compared with those of the CG-DM and CG-GC JAM-MOSFETs to show that the proposed structure has enhanced reliability against short channel effects (SCEs), hot carrier effects (HCEs) and various leakage currents (GIDL and gate leakage) for various control-to-screen gate length ratios. The proposed modeled results have been validated by comparing them with numerical data obtained by using a 3D commercial TCAD simulator.

Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability

Abstract This paper presents a 2-D analytical model of ultrathin hetero dielectric, asymmetric halo doped graded channel (HDGC) nanowire junctionless accumulation mode (JAM) MOSFETs obtained by incorporating the concepts of gate-oxide engineering (i.e., hetero dielectric) and channel engineering (i.e., graded channel) simultaneously. Superposition technique with appropriate boundary conditions has been used to solve Poisson's equation for determining the potential distribution function. The minimum central potential concept has been used to derive the threshold voltage of the HDGC-JAM MOSFETs including the quantum confinement effects. The performance of the proposed device has been compared with that of the uniformly doped JAM-MOSFETs. The proposed model also investigates the effect of control and screen gate length variations on short channel effects (SCEs) and hot carrier effects (HCEs) of the proposed device. Further, an analytical total drain current model considering the effects of gate induced drain leakage (GIDL) at negative bias has also been formulated.

Achieving Reduced Specific On-Resistance in 1.2 kV SiC Power MOSFETs at Elevated Temperature

Power MOSFETs operate at elevated temperatures due to self-heating and hot ambient temperatures. This paper analyzes the increase in on-resistance with temperature for 1.2 kV rated 4H-SiC planar MOSFETs. The impact of various structural parameters are studied using analytical models supported by experimental data. This work defines how to achieve a low ratio [Ron(150°C)/Ron(25°C)] by structural optimization of 1.2 kV SiC planar MOSFETs for the first time. It is found that the inversion mode MOSFETs, fabricated by us in a 6 inch commercial foundry, have a lower ratio [Ron(150°C)/Ron(25°C)] than the accumulation mode MOSFETs, due to a better balance of change in channel and bulk mobility with temperature. Compared with typical commercially available MOSFETs, our fabricated accumulation mode and inversion mode MOSFETs exhibit a lower ratio [Ron(150°C)/Ron(25°C)], resulting in superior HF-FOM [RonxQgd] at 150°C.

Carrier Mobility Enhancement by Applying Back-Gate Bias in Ge-on-Insulator MOSFETs

In this letter, we comprehensively study the carriers’ mobility and the effect of back-gate bias ( ${V} _{\textsf {bg}}$ ) in Ge-on-insulator (GeOI) MOSFETs with various working modes, including accumulation mode (AM) nMOSFET, inversion mode (IM) nMOSFET, AM pMOSFET, and IM pMOSFET. The results show that the AM nMOSFETs and pMOSFETs have higher drain currents and carriers’ mobility. The electron mobility increases under positive ${V} _{\textsf {bg}}$ and decreases under negative ${V} _{\textsf {bg}}$ . While the hole mobility has the opposite ${V} _{\textsf {bg}}$ dependence. The carriers’ mobility of AM MOSFETs is proved to benefit more from ${V} _{\textsf {bg}}$ due to the increase of carriers’ densities. The peak mobility enhancements of more than 100% for holes and 35% for electrons are achieved in GeOI MOSFETs by applying ${V} _{\textsf {bg}}$ .

Optimization of SiC UMOSFET Structure for Improvement of Breakdown Voltage and ON-Resistance

This paper proposes an optimized structure of 4H-SiC U-shaped accumulation-mode MOSFET (U-ACCUFET), which exhibits lower on-resistance and higher breakdown voltage. In this structure, an n-doped region is added underneath the gate trench, which covers the p+ shielding region. The new appended section spreads out the electrons to the bottom of the p+ shielding region and conducts the electrons in the downward direction. Output on-state characteristic curves ( ${I}_{\mathrm {DS}}$ – ${V}_{\textsf {DS}}$ ), on-resistance, transfer characteristic curves ( ${I}_{\textsf {DS}}$ – ${V}_{\textsf {GS}}$ ), threshold voltage ( ${V}_{t}$ ), subthreshold slope, and off-state characteristics of the optimized structure are observed. The proposed device shows on-resistance of 1.55 $\text{m}\Omega ~\cdot $ cm2 at ${V}_{\textsf {GS}}= \textsf {16}$ V and ${V}_{\textsf {DS}}= \textsf {1}$ V and breakdown voltage of 2624 V at ${V}_{\textsf {GS}}= \textsf {0}$ V. The simulation results indicate a superior performance of the optimized U-ACCUFET structure as the on-resistance reduces by 6% and breakdown voltage increases by 7.2% as compared with that of the conventional one. Also, the figure of merit ${V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ is improved by 21.6%.

Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

In this study, we investigate the electrical and noise performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers and compare them with conventional MOSFETs fabricated either on Si(100) or Si(110) wafers. With regard to electrical performances, accumulation-mode p-type MOSFETs are in every aspect superior. However, its n-type counterpart does not provide the best performances even though they are still superior to conventional transistors when fabricated on the same type of wafer. Conventional inversion-mode n-MOSFETs on Si(100) wafers still display the best performances. The simultaneous improvement and reduction in drivability respectively in the p- and n-type transistors make the accumulation-mode MOSFETs fabricated on Si(110) wafers extremely well suited for complementary technologies owing to their great balance in terms of drivability. With regard to noise evaluation, accumulation-mode MOSFETs on Si(110) wafers exhibit the highest noise level even though they compare relatively well with the inversion transistors on Si(110) wafers, especially for p-type ones. The lowest noise level is obtained for conventional inversion-mode MOSFETs on Si(100) wafers, and the type of wafer upon which transistors are fabricated is the reason. Indeed, the fabrication of high-quality Si/SiO2 interfaces is better achieved for silicon wafers with a (100) crystallographic orientation, leading to few interface defects and consequently less noise.

Impact of doping concentration on 1/f noise performances of accumulation-mode Si(100) n-MOSFETs

The superiority of highly doped accumulation-mode n-MOSFETs over the conventional inversion-mode ones has been acknowledged in this paper, not only in terms of electrical performances but also in terms of noise level. These results, in addition to those regarding accumulation-mode p-MOSFETs, demonstrate that an improved CMOS technology built on simultaneously high-speed and low-noise accumulation-mode MOSFETs has been achieved, paving the way towards more reliable and faster microprocessors.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (VT) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (@fs) to a value @fsT necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that @fsT. The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3x10^1^5-5x10^1^7/cm^3. Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature.

Accumulation-Mode MOSFET (AMOSFETs) Fabricated on Silicon Nanowires and Polysilicon Thin Films

Accumulation-mode MOSFET (AMOSFET) is an extremely simple FET configuration which can be used to fabricate high performance FETs on nanowires, nanoribbons and ultra-thin films. Unlike conventional FETs, AMOSFETs are majority carrier devices, and rely on the ability of the gate to accumulate or deplete a nanoscale thick channel region to turn the FET ON or OFF, respectively. AMOSFETs do not require heavily doped source/drain regions (no p-n junctions) or very thin gate dielectrics; this makes the device structure extremely easy and potentially inexpensive to fabricate. Our group has previously demonstrated AMOSFETs on VLS-grown SiNWs. In this report, we give an update on AMOSFET performance for devices fabricated on VLS-grown SiNWs and on polysilicon ultra-thin films as well.

(Invited) The Silicon Nanowire Accumulation-Mode MOSFETs

The accumulation-mode MOSFET (AMOSFET) is a very simple structured FET configuration which offers the potential for fabricating low cost, high performance FETs on semiconductor nanostructures. The configuration consists of a single doping type silicon nanowire, ohmic source and drain contacts, and a partially gated region. Despite their simple structure, AMOSFETs are capable of showing excellent device characteristics. AMOSFETs fabricated on undoped VLS-grown silicon nanowires exhibit transfer characteristics, with ION/IOFF ratios ~105, and subthreshold swings as low as 150 mV/dev. However, contrary to expectations, AMOSFETs fabricated on intentionally p-type doped silicon nanowires exhibit very poor transfer characteristics; this we attribute to a decrease in conductivity of the doped silicon nanowire upon oxidation. A new device structure, called the AMISFET is demonstrated, which overcomes the problems associated with oxidation of doped nanowires, and is capable of exhibiting good transfer characteristics for FETs fabricated on doped nanowires.

Impact of New Approach to Improve MOSFETs Performance with Ultrathin Gate Insulator

In this study, we focus on the difference behavior of the gate-channel capacitance (Cgc) characteristics in the inversion-mode (IM) and the accumulation-mode (AM) SOI MOSFETs. We experimentally demonstrate that the gate-channel capacitance in the AM MOS device is obviously larger than that in IM MOS device using the same gate insulator on the same wafer. The increase of the Cgc in AM MOSFETs is much more remarkable as downscaling the gate insulator due to the different inversion and accumulation layer quantization effect and poly-Si gate depletion effect. As the result, the current drivability has been obviously improved in the AM MOSFETs resulted from its vastly increased gate-channel capacitance, especially in the MOSFETs with the ultrathin gate insulator.

Low On-Resistance in Normally-Off 4H-SiC Accumulation MOSFET

In our previous paper [1], we simulated an accumulation-mode MOSFET with an epitaxial layer channel (epi-channel) that had a high channel mobility. In this paper, we experimentally show that channel mobility is enhanced by the epi-channel. On varying the thickness of the epi-channel, the channel mobility improved from a few cm2/Vs to 100 cm2/Vs. Finally, we show that the “Normally-off” accumulation MOSFET with a 720 V breakdown voltage has a low on-resistance (10.4 m1cm2) and that the 3 × 3 mm2 accumulation MOSFET operates over 10 A and its on-resistance is 19 m1cm2.

Novel SiC accumulation-mode power MOSFET

In this paper, a new structure of Silicon Carbide (SiC) accumulation-mode MOSFET (ACCUFET) for high-power applications has been proposed and analyzed. The novel ACCUFET utilizes fully depleted N-channel epilayer, grown on P-base epilayer, to achieve normally-off operation. A trench region is formed by etching and is implanted to create N-type path that connects the N-channel epilayer (accumulation channel) to underlaying N-drift region. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI two-dimensional (2-D) device simulator. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit (FOM) for power devices.