Access Latency Research Articles

Multiobjective Edge Server Placement in Mobile-Edge Computing Using a Combination of Multiagent Deep Q-Network and Coral Reefs Optimization

The growth of telecommunication technologies, especially 5G, the growing popularity of smart mobile devices, the emergence of smart cities and Internet of Things (IoT), and the easy use of these equipments have led the cloud users to utilize their various services. Real-time applications and the use of big data have caused cloud service providers (CSPs) to move their servers to the edge of the network and in the vicinity of users to maintain the quality of their services. For this purpose, the concept of mobile-edge computing (MEC) was formed. Applications often have heavy computing complexity on mobile devices or require a lot of data to process. Moreover, in order to save energy consumption of the batteries of this equipment, offloading them on the network resources can transfer the computational complexity from the users’ equipment to the network resources. The resource placement (RP) is one of the major challenges in this area. Improper resource topology upsets their load balancing and increases access latency. In the proposed method of this article, the cellular mobile network is divided into smaller areas and using the coral reefs optimization (CRO) algorithm, the optimal placement of resources in each of these areas will be locally performed. The deep <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -network (DQN) and Markov game (MG) are used to optimize global RP to reduce global latency and to improve resource load balancing as its two objectives. The results of the experiments show that the proposed method has significantly improved its objectives and server’s energy efficiency, compared to some similar works in this area.

TB-NUCA: A Temperature-Balanced 3D NUCA Based on Bayesian Optimization

Three-dimensional network-on-chip (NoC) is the primary interconnection method for 3D-stacked multicore processors due to their excellent scalability and interconnect flexibility. With the support of 3D NoC, 3D non-uniform cache architecture (NUCA) is commonly used to organize the last-level cache (LLC) due to its high capacity and fast access latency. However, owing to the layered structure that leads to longer heat dissipation paths and variable inter-layer cooling efficiency, 3D NoC experiences a severe thermal problem that has a big impact on the reliability and performance of the chip. In traditional memory-to-LLC mapping in 3D NUCA, the traffic load in each node is inconsistent with its heat dissipation capability, causing thermal hotspots. To solve the above problem, we propose a temperature-balanced NUCA mapping mechanism named TB-NUCA. First, the Bayesian optimization algorithm is used to calculate the probability distribution of cache blocks in each node in order to equalize the node temperature. Secondly, the structure of TB-NUCA is designed. Finally, comparative experiments were conducted under random, transpose-2, and shuffle traffic patterns. The experimental results reveal that, compared with the classical NUCA mapping mechanism (S-NUCA), TB-NUCA can increase the mean-time-to-failure (MTTF) of routers by up to 28.13% while reducing the maximum temperature, average temperature, and standard deviation of temperature by a maximum of 4.92%, 4.48%, and 20.46%, respectively.

Evaluation of Hash Join Operations Performance Executing on SDN Switches: A Cost Model Approach

Distributed database systems store and manipulate data on multiple machines. In these systems, the processing cost of query operations is mainly impacted by the data access latency between machines over the network. With recent technology advances in programmable network devices, the network switches provide new opportunities for dynamically managing the network topology, enabling the data processing on these devices with the same network throughput. In this paper, we explore the programmable network switches in query processing, evaluating the processing performance of a cost model in executing the hash join operation. We assume the storage of the hash table built from outer relation and the materialization of the join probing are made in switches using advanced matching techniques similar to package inspections enabled by Ternary Content-Addressable Memories (TCAM) or SRAM via hashing. Our results show that processing the hash join operation using network switches achieved the best results compared to traditional servers, with an average time reduction of 91.82% (Query-10 from TPC-H) and 96.52% (Query-11 from TPC-H).

PPOAccel: A High-Throughput Acceleration Framework for Proximal Policy Optimization

Reinforcement Learning (RL) is a major branch of AI that enables agents to learn optimal decision making via interaction with the environment. Proximal Policy Optimization (PPO) is the state-of-the-art policy optimization based RL algorithm which achieves superior overall performance on various benchmarks. A PPO agent iteratively optimizes its policy - a function which chooses optimal actions approximated by a DNN, with each iteration consisting of two computationally intensive phases: Sample Generation - where agents inference on its policy and interact with the environment to collect data, and Model Update - where the policy is trained using the collected data. In this paper, we develop the first high-throughput PPO accelerator on CPU-FPGA heterogeneous platform. Our unified systolic-array based design accelerates both the inference and the training of the deep neural network used in a RL algorithm, and is generalizable to various MLP and CNN models across a wide range of RL applications. We develop novel optimizations to simultaneously reduce data access and computation latencies, specifically: (a) optimal data flow mapping to systolic array, (b) novel memory-blocked data layout to enable streaming stall-free data access in both forward and backward propagations, and, (c) a systolic array compute sharing technique to mitigate load imbalance in the training of two networks. We evaluate our design on widely used robotics and gaming benchmarks, achieving 1.4×–26× and 1.3×–2.7× improvements in throughput, respectively, when compared with state-of-the-art CPU/CPU-GPU implementations.

Intelligent Replica Selection in Edge and IoT Environments Using Artificial Neural Networks

Cloud, edge and Internet of Things (IoT) technologies have emerged to overcome the challenges involved in sharing computational resources and information services. Within generic cloud systems, two models have been identified as having widespread applicability: computation clouds and data clouds. A data cloud is cloud computing that aims to manage, unify and operate multiple data workloads. Many current applications generate datasets consisting of petabytes (PB) of information. Managing large datasets is a complex issuel; in particular, datasets associated with many applications can be distributed widely in geographical terms, particularly in IoT systems. Edge and IoT systems are facing new challenges with increased complexity, making scalability an important issue that will affect the performance of the system. Data replication services are widely accepted techniques to improve availability and fault tolerance, and to improve the data access time. Current replication services, however, often exhibit an increase in response time, reflecting the problems associated with the ever-increasing size of databases. This paper proposes a prediction model to predict replica locations using the files’ access profile, which feeds the neural networks with the access and location behavior (file profile) to minimize the overhead of transferring large volumes of data, which slows down the system and requires careful management. This new model has shown high accuracy and low overheads. The result shows a significant improvement in total task execution time using the proposed model for locating files by 16.34% and 30.45%; in addition, the results show bandwidth improvement by 24.7% and 49.4% compared to the user profile prediction model and replica service model without prediction, respectively. Consequently, the proposed algorithm can improve data access speed, reduce data access latency and decrease bandwidth consumption.

Beaconnect

Content delivery networks (CDNs) are critical for minimizing access latency in the Web as they efficiently distribute online resources across the globe. But since CDNs can only be enabled on the scope of entire websites (and not for individual users or user groups), the effects of page speed acceleration are often quantified with potentially skewed before-after comparisons rather than statistically sound A/B tests. We introduce the system Beaconnect for collecting and analyzing Web performance data without being subject to these limitations. Our contributions are threefold. First, Beaconnect is natively compatible with A/B testing Web performance as it is built for a custom browser-based acceleration approach and thus does not rely on traditional CDN technology. Second, we present our continuous aggregation pipeline that achieves sub-minute end-to-end latency. Third, we describe and evaluate a scheme for continuous real-time reporting that is especially efficient for large customers and processes data from over 100 million monthly users at Baqend.

Exploring the Non-Overlapping Visibility Regions in XL-MIMO Random Access and Scheduling

The recent extra-large scale massive multiple-input multiple-output (XL-MIMO) systems are seen as a promising technology for providing very high data rates in high user-density scenarios. Spatial non-stationarities and visibility regions (VRs) appear across the XL-MIMO array, since its large dimension is of the same order of the distances to the user-equipments (UEs). Due to the increased density of UEs in typical applications of XL-MIMO systems and the scarcity of pilots, the design of random access (RA) protocols and scheduling algorithms become challenging. In this paper, we propose a joint RA and scheduling protocol, namely non-overlapping VR XL-MIMO (NOVR-XL) RA protocol, which takes advantage of the different VRs of the UEs for improving RA performance, besides of seeking UEs with non-overlapping VRs to be scheduled in the same payload data pilot (PDP) resource. Our results reveal that the proposed scheme achieves significant gains in terms of sum-rate compared with traditional RA schemes, as well as reducing access latency and improving connectivity performance as a whole.

A Novel Decomposed Optical Architecture for Satellite Terrestrial Network Edge Computing

Aiming at providing a high-performance terrestrial network for edge computing in satellite networks, we experimentally demonstrate a high bandwidth and low latency decomposed optical computing architecture based on distributed Nanoseconds Optical Switches (NOS). Experimental validation of the decomposed computing network prototype employs a four-port NOS to interconnect four processor/memory cubes. The SOA-based optical gates provide an ON/OFF ratio greater than 60 dB, enabling none-error transmission at a Bit Error Rate (BER) of 1 × 10−9. An end-to-end access latency of 122.3 ns and zero packet loss are obtained in the experimental assessment. Scalability and physical performance considering signal impairments when increasing the NOS port count are also investigated. An output OSNR of up to 30.5 dB and an none-error transmission with 1.5 dB penalty is obtained when scaling the NOS port count to 64. Moreover, exploiting the experimentally measured parameters, the network performance of NOS-based decomposed computing architecture is numerically assessed under larger network scales. The results indicate that, under a 4096-cube network scale, the NOS-based decomposed computing architecture achieves 148.5 ns end-to-end latency inside the same rack and zero packet loss at a link bandwidth of 40 Gb/s.

HTIDB: Hierarchical Time-Indexed Database for Efficient Storage and Access to Irregular Time-series Health Sensor Data.

With the enormous amount of data collected by unobtrusive sensors, the potential of utilizing these data and applying various multi-modal advanced analytics on them is numerous and promising. However, taking advantage of the ever-growing data requires high-performance data-handling systems to enable high data scalability and easy data accessibility. This paper demonstrates robust design, developments, and techniques of a hierarchical time-indexed database for decision support systems leveraging irregular and sporadic time series data from sensor systems, e.g., wearables or environmental. We propose a technique that leverages the flexibility of general purpose, high-scalability database systems, while integrating data analytics focused column stores that leverage hierarchical time indexing, compression, and dense raw numeric data storage. We have evaluated the performance characteristics and tradeoffs of each to understand the data access latencies and storage requirements, which are key elements for capacity planning for scalable systems.

DNA Pre-Alignment Filter Using Processing Near Racetrack Memory

Recent DNA <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pre-alignment</i> filter designs employ DRAM for storing the reference genome and its associated meta-data. However, DRAM incurs increasingly high energy consumption of background and refresh energy as devices scale. To overcome this problem, this paper explores a design with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">racetrack memory</i> (RTM)–an emerging non-volatile memory that promises higher storage density, faster access latency, and lower energy consumption. Multi-bit storage cells in RTM are inherently sequential and thus require data placement strategies to mitigate the performance and energy impacts of shifting during data accesses. We propose a near-memory pre-alignment filter with a novel data mapping and several shift reduction strategies designed explicitly for RTM. On a set of four input genomes from the 1000 Genome Project, our approach improves performance and energy efficiency by 68% and 52%, respectively, compared to the state-of-the-art DRAM-based architecture.

Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures

Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures place simple cores close to DRAM banks. Recent research demonstrates that they can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwidth and low memory access latency, thereby being a good fit to accelerate the Sparse Matrix Vector Multiplication (SpMV) kernel. SpMV has been characterized as one of the most significant and thoroughly studied scientific computation kernels. It is primarily a memory-bound kernel with intensive memory accesses due its algorithmic nature, the compressed matrix format used, and the sparsity patterns of the input matrices given. This paper provides the first comprehensive analysis of SpMV on a real-world PIM architecture, and presents SparseP, the first SpMV library for real PIM architectures. We make two key contributions. First, we design efficient SpMV algorithms to accelerate the SpMV kernel in current and future PIM systems, while covering a wide variety of sparse matrices with diverse sparsity patterns. Second, we provide the first comprehensive analysis of SpMV on a real PIM architecture. Specifically, we conduct our rigorous experimental analysis of SpMV kernels in the UPMEM PIM system, the first publicly-available real-world PIM architecture. Our extensive evaluation provides new insights and recommendations for software designers and hardware architects to efficiently accelerate the SpMV kernel on real PIM systems. For more information about our thorough characterization on the SpMV PIM execution, results, insights and the open-source SparseP software package [21], we refer the reader to the full version of the paper [3, 4]. The SparseP software package is publicly and freely available at https://github.com/CMU-SAFARI/SparseP.

Security Model for Randomization-based Protected Caches

Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention.This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question.In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache sidechannel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.

Performance analysis of cognitive radio‐assisted clustering car‐following V2X communication system

SummaryIn this paper, we study high spectrum efficiency transmission in vehicle to everything (V2X) system to allow the roadside unit (RSU) broadcasts its safety information to vehicles which belong to a dedicated group. However, low latency and high reliability are tightly required in related applications of V2X; we explore advantages of cognitive radio (CR) and non‐orthogonal multiple access (NOMA) to form system, namely, CR NOMA‐V2X. Such considered system provides transmissions from the RSU to vehicles with respect to lower access latency and to enhance the packet reception probability. In the proposed scheme, the vehicles need channel state information (CSI) for signal decoding order, but we face with imperfect CSI occurs in practical scenarios. To evaluate such degraded system performance of the involved CR NOMA‐V2X, we introduce the approximate closed‐form expressions of outage probability. Numerical results indicate the validness of our derivations.

VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors

Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively hides the memory access latencies for multi-threaded graph workloads provided that sufficient threads are supported in hardware. Unfortunately, providing a sufficiently large number of physical threads incurs an unjustifiably high hardware cost for commodity SMT processors which typically implement only two physical hardware threads. Ideally, we would like to achieve aggressive-SMT performance when running graph workloads on modest commodity processors. In this paper, we propose Virtualized Multi-Threading (VMT), a low-overhead multi-threading paradigm for accelerating graph workloads on commodity processors. Unlike prior multi-threading paradigms, VMT virtualizes both the physical hardware threads and the architecture state: VMT maps a large number of logical software threads to a small number of physical hardware threads, while maintaining the architecture state of the logical threads in the processor's cache hierarchy. Implemented on top of a quad-core 2-way SMT processor, VMT achieves an average speedup of 1.74× for a set of representative graph workloads, while incurring minimal hardware cost (195 bytes per core to support up to 32 logical threads). VMT's low hardware cost paves the way for implementation in commodity processors.

Joint Optimization of IRS and UAV-Trajectory: For Supporting Statistical Delay and Error-Rate Bounded QoS Over mURLLC-Driven 6G Mobile Wireless Networks Using FBC

Massive ultra-reliable and low-latency communications (mURLLC) has been developed as a new and dominating 6G-standard services to support statistical quality of service (QoS) provisioning while raising several major design issues, including massive connectivity, ultra-low latency, and super-reliability. Correspondingly, a number of emerging 6G candidate enablers, including statistical delay and error-rate bounded QoS provisioning, finite blocklength coding (FBC), intelligent reflecting surfaces (IRS), unmanned aerial vehicle (UAV), etc., have been developed to support mURLLC. Specifically, due to the potential improvements in coverage capability as well as the spectral efficiency, both IRS and UAV have been widely proposed to reconfigure wireless propagation environments to compensate for blocked line-of-sight (LOS) communication links and create controllable and smart radio environments. In addition, to solve the massive connectivity issues imposed by mURLLC, integrating UAV with IRS provides a promising means to significantly enhance LOS coverage due to the relatively high altitude and 3D mobility of the UAVs. However, although small-packet communications enabled by FBC are usually employed for massive access to reduce access latency and decoding complexity, how to upper-bound both delay and error rate while efficiently supporting mURLLC in IRS-UAV-integrated systems still remains a challenging problem.

Optimal Caching for Low Latency in Distributed Coded Storage Systems

Erasure codes have been widely considered as a promising solution to enhance data reliability at low storage costs. However, in modern geo-distributed storage systems, erasure codes may incur high data access latency as they require data retrieval from multiple remote storage nodes. This hinders the extensive application of erasure codes to data-intensive applications. This paper proposes novel caching schemes to achieve low latency in distributed coded storage systems. Assuming that future data popularity and network latency information are available, an offline caching scheme is proposed to explore the optimal caching solution for low latency. The proposed scheme categorizes all feasible caching decisions into a set of cache partitions, and then obtains the optimal caching decision through market clearing price for each cache partition. Furthermore, guided by the optimal scheme, an online caching scheme is proposed according to the measured data popularity and network latency information in real time, without the need to completely override the existing caching decisions. Both theoretical analysis and experiment results demonstrate that the online scheme can approximate the offline optimal scheme well with dramatically reduced computation complexity.

TEE-Watchdog: Mitigating Unauthorized Activities within Trusted Execution Environments in ARM-Based Low-Power IoT Devices

Trusted execution environments (TEEs) are on the rise in devices all around us ranging from large-scale cloud-based solutions to resource-constrained embedded devices. With the introduction of ARM TrustZone-M, hardware-assisted trusted execution is now supported in IoT nodes. TrustZone-M provides isolated execution of security-critical operations and sensitive data-generating peripherals. However, TrustZone-M, like all other TEEs, does not provide a mechanism to monitor operations in the trusted areas of the device and software in the secure areas of an IoT device has access to the entire secure and nonsecure software stack. This is crucial due to the diversity of device manufacturers and component suppliers in the market, which manifests trust issues, especially when third-party peripherals are incorporated into a TEE. Compromised TEEs can be misused for industrial espionage, data exfiltration through system backdoors, and illegal data sharing. It is of utmost importance here that system peripheral behaviour in terms of resource access is in accordance with their intended usage that is specified during integration. We propose TEE-Watchdog, a lightweight framework that establishes MPU protections for secure system peripherals in TrustZone-enabled low-end IoT devices. TEE-Watchdog ensures blocking unauthorized peripheral accesses and logging of application misbehaviour running in the TEE based on a manifest file. We define lightweight specifications and structure for the application manifest file enlisting permissions for critical system peripherals using concise binary object representation (CBOR). We implement and evaluate TEE-Watchdog using a Musca-A2 test chipboard. Our microbenchmark evaluations on CPU time and RAM usage demonstrated the practicality of TEE-Watchdog. Securing the system peripherals using TEE-Watchdog protections induced a 1.4% overhead on the latency of peripheral accesses, which was 61 microseconds on our test board. Our optimized CBOR-encoded manifest file template also showed a decrease in manifest file size by 40% as compared to the standard file formats, e.g., JSON.

A tail-tolerant cloud storage scheduling based on precise periodicity detection

Cloud storage is a fundamental component of the cloud computing system, which significantly affects the overall performance and quality of service of the cloud. Cloud storage servers face the challenge of imbalanced workloads. According to our observations on the time series generated by cloud storage, we found that the imbalance workloads will dramatically increase the tail latency of data access in the multi-tenant scenario. The intuitive solution is to periodicity detect the imbalance storage nodes and re-balance the loads. However, there are four challenges to accurately detect load of storage in the cloud with multiple tenants since the load may change frequently in cloud. This paper proposes PrecisePeriod, a precise periodicity detection algorithm customized for multi-tenant cloud storage. It removes outliers through data preprocessing, employs the discrete wavelet transform to remove high-frequency noise while keeping frequency domain information, computes the candidate periodicity queue using the autocorrelation function, and determines precise period through periodicity verification. Then, we design a cloud storage load balancing scheduling strategy based on PrecisePeriod, and the evaluation shows that the PrecisePeriod scheduling significantly reduces tail latency while only bringing 1-2% overhead.

Achieving Low Latency in Massive Access: A Mean-Field Approach

The next generation massive access has attracted considerable recent attention due to its potential in smart meters, industrial internet of things (IIoT), and smart traffics, etc. However, how to achieve the minimum queuing delay in massive access still remains open, thereby making quality-of-service (QoS) assurance a challenging issue in practice. In this paper, we aim at minimizing the average queuing delay by applying cross-layer scheduling with joint channel and buffer awareness, the complexity of which increases exponentially with the number of users. Fortunately, with massive users or devices, mean-field approximation can be adopted to substantially simplify the design and analysis of the delay-optimal scheduling. More specifically, we present a cocktail filling policy and a queue-aware multiuser diversity protocol, in which all backlogged packets of a user will be served by either NOMA or TDMA mode respectively, if the user’s channel gain is beyond a certain threshold. The average queuing delay and queue-length-violation probability are derived based on a Markov model. Numerical results will also demonstrate that the mean-field approximation based joint physical and network layer scheduling is capable of improving the QoS in massive access.

PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory

Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturb, and lower access latency. Despite these advantages, 3D flash memory brings a number of new challenges. First, in 3D flash memory, NAND strings punch through multiple stacked layers to form the 3D infrastructure. Current etching process is unable to manufacture perfect channels with identical feature size. Second, with more stacked layers, the cell current in 3D flash memory is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D flash memory. This article present <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PVSensing</i> , a process-variation-aware space allocation strategy for open-channel SSD with 3D charge-trap flash memory. PVSensing is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PVSensing utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. Three reliability enhancement strategies (i.e., the adaptive creation of fault cubes, the physical block mining, and the live migration of write requests) are proposed. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PVSensing can effectively reduce uncorrectable bit errors, and improve the reliability of critical data with negligible extra erase operations in comparison with representative schemes.