Access Conflicts Research Articles

Cooperative control and communication of connected vehicles considering packet dropping rate

ABSTRACTThis paper investigates cooperative control and communication scheduling of a platoon of connected vehicles. Considering the effect of packet dropout and the network access limitation, the vehicular platoon is modelled as a discrete-time switching system. We obtain a set of sufficient conditions (where the rate of different platoon control modes is factored in) for string stability and schedulability of the vehicular platoon. A unified framework of network access scheduling and platoon control is proposed, which can guarantee string stability of the platoon of vehicles and resolve network access conflicts among them. Both numerical simulations and experimental studies with laboratory-scale cars have demonstrated the effectiveness of the presented co-design algorithm.

Pinpointing and scheduling access conflicts to improve internal resource utilization in solid-state drives

Modern solid-state drives (SSDs) are integrating more internal resources to achieve higher capacity. Parallelizing accesses across internal resources can potentially enhance the performance of SSDs. However, exploiting parallelism inside SSDs is challenging owing to real-time access conflicts. In this paper, we propose a highly parallelizable I/O scheduler (PIOS) to improve internal resource utilization in SSDs from the perspective of I/O scheduling. Specifically, we first pinpoint the conflicting flash requests with precision during the address translation in the Flash Translation Layer (FTL). Then, we introduce conflict eliminated requests (CERs) to reorganize the I/O requests in the device-level queue by dispatching conflicting flash requests to different CERs. Owing to the significant performance discrepancy between flash read and write operations, PIOS employs differentiated scheduling schemes for read and write CER queues to always allocate internal resources to the conflicting CERs that are more valuable. The small dominant size prioritized scheduling policy for the write queue significantly decreases the average write latency. The high parallelism density prioritized scheduling policy for the read queue better utilizes resources by exploiting internal parallelism aggressively. Our evaluation results show that the parallelizable I/O scheduler (PIOS) can accomplish better SSD performance than existing I/O schedulers implemented in both SSD devices and operating systems.

Approach and impact of a participatory process for the reorganization of irrigation management: a case study in Indonesia

The paper emphasizes key lessons learnt about a research intervention implemented from 2006 to 2009 to solve water access conflicts in the Klaten irrigated rice production area (Central Java, Indonesia). To make stakeholders’ involvement easier, to empower them and build their capacity, action research was carried out according to a flexible and iterative approach. Each step involved a cycle of diagnosis, action planning, implementation, evaluation and learning. The paper shows the need to facilitate the functioning of a multi-stakeholder platform through the creation of a monitoring mechanism in order to ensure, on the one hand, stakeholders’ involvement within the action-research process and on the other hand, foster brainstorming and mutual learning among participants. The paper brings to the fore the usefulness of assessing findings of multidisciplinary and participatory appraisals through modeling and geo-referenced mapping tools in order to facilitate collective learning, negotiation and technical and institutional innovation. Finally, through the assessment of the evolution of the farmers’ association, whose creation was a project outcome, the paper reflects about key issues and key steps that have contributed to carry on successfully the developed methodology.

Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives

Solid state drives (SSDs) have been widely deployed in personal computers, data centers, and cloud storages. In order to improve performance, SSDs are usually constructed with a number of channels with each channel connecting to a number of nand flash chips, each flash chip consisting of multiple dies and each die containing multiple planes. Based on this parallel architecture, I/O requests are potentially able to access parallel units simultaneously. Despite the rich parallelism offered by the parallel architecture, recent studies show that the utilization of flash parallel units is seriously low. This paper shows that the low parallel unit utilization is highly caused by the access conflict among I/O requests. In this paper, we propose parallel issue queueing (PIQ), a novel I/O scheduler at the host systems. PIQ groups I/O requests without conflicts into the same batch and I/O requests with conflicts into different batches. Hence, the multiple I/O requests in one batch can be fulfilled simultaneously by exploiting the rich parallelism of SSDs. Extensive experimental results show that PIQ delivers significant performance improvement especially for the applications which have heavy access conflicts.

Energy Optimal Task Scheduling with Normally-off Local Memory and Sleep-aware Shared Memory with Access Conflict

The rapid development of the Real-Time and Embedded System (RTES) has increased the requirement on the processing capabilities of sensors, mobiles and smart devices, etc. Meanwhile, energy efficiency techniques are in desperate need as most devices in RTES are battery powered. Following the above trends, this work explores the memory system energy efficiency for a general multi-core architecture. This architecture integrates a local memory in each processing core, with a large off-chip memory shared among multiple cores. Decisions need to be made on whether tasks will be executed with the shared memory or the local memory to minimize the total energy consumption within real-time constraints. This paper proposes optimal schemes as well as a polynomial-time approximation algorithm with constant ratio. The problem complexity analysis for different task and system models is also presented. Experimental results show that the proposed approximation scheme performs close to the optimal solution in average.

Aðgengi fullorðinna að námi á framhaldsskólastigi: Stofnana- og aðstæðubundnar hindranir á menntavegi

Markmið þessarar rannsóknar var að kanna hvaða hindranir mæta fullorðnu fólki sem hefur hug á að ljúka námi á framhaldsskólastigi. Tekin voru viðtöl við átta einstaklinga á aldrinum 25–30 ára sem stunda nám á vegum framhaldsfræðslunnar og eru í aðfaranámi. Í frásögnum þeirra vógu aðstæðu- og stofnanabundnar hindranir mun þyngra en viðhorfsbundnar hindranir. Helsta hindrun nemendanna var fjármögnun námsins þar sem unga fólkið býr við þröngan fjárhag og er með fjölskyldu á framfæri. Flókið reyndist að samþætta fjölskyldulíf og vinnu með námi og það skapaði mikið álag í lífi þess. Einnig kom fram að upplýsingar um nám og fjárstuðning í boði eru oft óljósar og viðmælendur töldu að framboð og skipulag náms kæmi ekki nægjanlega til móts við þarfir þeirra fyrir stuðning og sveigjanleika. Þátttakendur sýndu frumkvæði og þrautseigju við að yfirstíga margvíslegar hindranir sem þeir mættu á menntaveginum. Hvatinn að rannsókninni er ekki síst sá að stjórnvöld hafa sett markmið um hærra menntunarstig þjóðarinnar en afar hægt gengur að ná þeim markmiðum. Rannsóknin getur því nýst stjórnvöldum við stefnumótun og menntastofnunum og aðilum fullorðinsfræðslu við að fækka stofnana- og aðstæðubundnum hindrunum á vegi fullorðinna námsmanna.

Exploiting Chip Idleness for Minimizing Garbage Collection—Induced Chip Access Conflict on SSDs

Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear leveling induced read, write, and erase operations, to solve the issues of inability of in-place updates and limited lifetime. When internal activities are triggered on a chip, the chip will be blocked. Our preliminary studies on several workloads show that when internal activities are frequently triggered, the host I/O performance will be significantly impacted because of the access conflict between them. In this work, in order to improve the access conflict induced performance degradation, a novel access conflict minimization scheme is proposed. The basic idea of the scheme is motivated by an interesting observation in SSDs: several chips are idle when other chips are busy with internal activities and host I/O requests. Based on this observation, we propose to schedule internal activities induced operations for minimized access conflict by exploiting the idleness of the multiple chips of SSDs. This approach is realized by two steps: First, read internal activities accessed data to the controller; second, by exploiting the idle chips during internal activities, write internal activities accessed data back to these idle chips. With this scheme, the internal activities can be processed with minimized access conflict to the host requests. Simulation results show that the proposed approach significantly reduces the access conflict, and in turn leads to a significant performance improvement of SSDs.

Minimising Access Conflicts on Shared Multi-Bank Memory

A common multi-core pattern consists of processors communicating through shared, multi-banked on-chip memory. Two approaches exist: Interleaved address mapping, which spreads consecutive data over all banks, and contiguous address mapping, which stores consecutive data on a single bank. In this work, we compare both approaches on the Kalray MPPA-256 platform. For contiguous mapping, we propose an algorithm, based on graph colouring techniques, to automatically perform the assignment of data blocks to memory banks with the goal of minimising access collisions and delays. Experiments with representative, parallel real-world benchmarks show that 69% of the tested configurations, when optimised for contiguous mapping by our algorithm, run up to 86% faster on average than with interleaved mapping.

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

Coarse-grained reconfigurable architecture (CGRA) is a promising architecture with high performance, high power-efficiency and attraction of flexibility. The computation-intensive parts of an application (e.g., loops) are often mapped on CGRA for acceleration. Due to the high parallel data access demands, the architecture with multi-bank memory is proposed to improve parallelism. For CGRA with multi-bank memory, a joint solution, which simultaneously considers the memory partitioning and modulo scheduling, is proposed to achieve a valid mapping with better performance. In this solution, the modulo scheduling and operator scheduling are used to achieve a valid loop mapping and a valid data placement without any memory access conflicts. By avoiding the pipelining stalls caused by conflicts, the performance of loop mapping is greatly improved. The experimental results on benchmarks of the Livermore, Polybench and Mediabench show that our approach can improve the performance of loops on CGRA to 1.89 $\times$ , 1.49 $\times$ and 1.37 $\times$ compared with REGIMap, HTDM and REGIMap with memory partitioning, at cost of an acceptable increase in compilation time.

Comparing Instructional Factors Related to Students’ Academic Self-Discipline in Norway and Finland

School learners can struggle with setting and striving for objectives that require sustained academic self‐discipline. We believe that teachers’ instructional qualities and school culture are factors that can successfully elicit students’ self-discipline in their academic work. This study explores and compares factors related to students’ academic self-discipline among Norwegian and Finnish youths at the upper secondary level. The Finnish students’ excellent results on international comparative tests have led many commentators to consider the Finnish model of education very worthy of emulation. Another reason to com-pare these two groups is that Finnish and Norwegian classrooms differ in their levels of in-class Internet access and computer use for learning purposes. From this perspective, it is interesting to compare empirical associations between instructional factors (as well as students’ school appreciation) and students’ academic self-discipline. The instructional factors in our theoretical model were teachers’ classroom management, teaching quality, teachers’ expressed expectations and the value students placed on the school as an institution. A total of 1433 urban Finnish and Norwegian upper secondary students in general study programmes participated in our cross-sectional questionnaire. We used structural equation modelling for our analysis, and the results show that the associations between instructional qualities (quality instruction, classroom management and high expectations) and academic self-discipline are overall stronger in the Finnish sample than the Norwegian sample. However, students’ appreciation for school was more highly associated with academic self-discipline in Norway than in Finland. Furthermore, the associations between in-class Internet access and motivational conflict were clearly higher in the Norwegian sample than in the Finnish sample. In both samples, we found strong associations between motivational conflict and academic self-discipline. We also discuss the meaning of these results and their implications for research and practice.

A Deep Collaborative Computing Based SAR Raw Data Simulation on Multiple CPU/GPU Platform

The outstanding computing ability of a graphics processing unit (GPU) brings new vitality to the typical computing intensive issue, so does the synthetic aperture radar (SAR) raw data simulation, which is a fundamental problem in SAR system design and imaging research. However, the computing power of a CPU was underestimated, and the tunings for a CPU-based method were missing in the previous works. Meanwhile, the collaborative computing of multiple CPUs/GPUs was not exploited thoroughly. In this paper, we propose a deep multiple CPU/GPU collaborative computing framework for time-domain SAR raw data simulation, which not only introduces the advanced vector extension (AVX) method to improve the computing efficiency of a multicore single instruction multiple data CPU, but also achieves a satisfactory speedup in the CPU/GPU collaborative simulation by fine-grained task partitioning and scheduling. In addition, an irregular reduction based SAR coherent accumulation approach is proposed to eliminate the memory access conflict, which is the most difficult issue in the GPU-based raw data simulation. Experimental results show that the multicore vector extension method greatly improves the computing power of a CPU-based method through about 70× speedup, thereby outperforming the single GPU simulation. Correspondingly, compared with the baseline sequential CPU approach, the multiple CPU/GPU collaborative simulation achieves up to 250× speedup. Furthermore, the irregular reduction based atomic-free optimization boosts the performance of the single GPU method by 20% acceleration. These results prove that the deep multiple CPU/GPU collaborative method is promising, especially for the case of huge volume raw data simulation with a wide swath and high resolution.

Enabling LTE and WiFi Coexisting in 5 GHz for Efficient Spectrum Utilization

Due to the increasing mobile traffic demands in cellular network, researchers have proposed the coexistence of LTE and WiFi technologies in 5 GHz unlicensed bands. Therefore, how to efficiently utilize the spectrum in 5 GHz becomes extremely important. To avoid the channel access conflicts, current LTE Unlicensed (LTE-U) technology introduces the duty cycle of LTE, while License-Assisted Access (LAA) technology introduces Listen-Before-Talk (LBT) mechanism. While these two technologies improve the spectrum utilization by using time division access schema, we believe that more efficient spectrum utilization can be achieved by enabling simultaneous transmissions from LTE and WiFi. In this paper, we propose a novel method (i.e.,Low Amplitude Stream Injection (LASI) method) to enable the simultaneous transmissions of WiFi and LTE frames in the same channel and recover the data from the conflicts. To further utilize theLASImethod, we introduce theConflict-Tolerant Channel Allocation (CTCA)algorithm to optimize the channel allocation and achieve more efficient spectrum utilization in 5 GHz. Extensive simulation results show that our approach achieves lower latency and higher throughput. Compared with the state-of-the-art LTE-U and LAA technologies, our approach can improve the spectrum efficiency 2.9 times.

Hybrid STM/HTM for nested transactions on OpenJDK

Transactional memory (TM) has long been advocated as a promising pathway to more automated concurrency control for scaling concurrent programs running on parallel hardware. Software TM (STM) has the benefit of being able to run general transactional programs, but at the significant cost of overheads imposed to log memory accesses, mediate access conflicts, and maintain other transaction metadata. Recently, hardware manufacturers have begun to offer commodity hardware TM (HTM) support in their processors wherein the transaction metadata is maintained "for free" in hardware. However, HTM approaches are only best-effort : they cannot successfully run all transactional programs, whether because of hardware capacity issues (causing large transactions to fail), or compatibility restrictions on the processor instructions permitted within hardware transactions (causing transactions that execute those instructions to fail). In such cases, programs must include failure-handling code to attempt the computation by some other software means, since retrying the transaction would be futile. Thus, a canonical use of HTM is lock elision : replacing lock regions with transactions, retrying some number of times in the case of conflicts, but falling back to locking when HTM fails for other reasons. Here, we describe how software and hardware schemes can combine seamlessly into a hybrid system in support of transactional programs, allowing use of low-cost HTM when it works, but reverting to STM when it doesn't. We describe heuristics used to make this choice dynamically and automatically, but allowing the transition back to HTM opportunistically. Our implementation is for an extension of Java having syntax for both open and closed nested transactions, and boosting, running on the OpenJDK, with dynamic injection of STM mechanisms (into code variants used under STM) and HTM instructions (into code variants used under HTM). Both schemes are compatible to allow different threads to run concurrently with either mechanism, while preserving transaction safety. Using a standard synthetic benchmark we demonstrate that HTM offers significant acceleration of both closed and open nested transactions, while yielding parallel scaling up to the limits of the hardware, whereupon scaling in software continues but with the penalty to throughput imposed by software mechanisms.

Securing Loosely-Coupled Collaboration in Cloud Environment through Dynamic Detection and Removal of Access Conflicts

Online collaboration service has become a popular offering of present day Software-as-a-Service (SaaS) clouds. It facilitates sharing of information among multiple participating domains and accessing them from remote locations. Owing to loosely-coupled nature of such collaborations, access request from a remote user is made in the form of a set of permissions. The cloud vendor maps the requested permissions into appropriate local roles in order to allow resource access. However, coexistence of such multiple simultaneous role activation requests may introduce conflicts which violate the principle of security. In this paper, we propose a distributed secure collaboration framework which enables collaborating domains to detect and remove these conflicts. Two features of our framework are: (i) it requires only local information, and (ii) it detects and removes conflicts on-the-fly. Formal proofs have been provided to establish the correctness of our approach. Experimental results and qualitative comparison with related work demonstrate the efficacy of our approach in terms of response time, thus addressing the scalability requirement of cloud services.

Communication Scheduling and Control of a Platoon of Vehicles in VANETs

This paper is concerned with the problem of vehicular platoon control in vehicular ad hoc networks subject to capacity limitation and random packet dropouts. By introducing binary sequences as the basis of network access scheduling and modeling random packet dropouts as independent Bernoulli processes, we derive a closed-form methodology for vehicular platoon control. In particular, an interesting framework for network access scheduling and platoon control codesign is established based on a set of priority rules for network access control. The resulting platoon control and scheduling algorithm can resolve network access conflicts in vehicular ad hoc networks and guarantee string stability and zero steady-state spacing errors. The effectiveness of the method is demonstrated by numerical simulations and experiments with laboratory-scale Arduino cars.

Historical Spectrum Sensing Data Mining for Cognitive Radio Enabled Vehicular Ad-Hoc Networks

In vehicular ad-hoc network (VANET), the reliability of communication is associated with driving safety. However, research shows that the safety-message transmission in VANET may be congested under some urgent communication cases. More spectrum resource is an effective way to solve transmission congestion. Hence, we introduce cognitive radio (CR) enabled VANET (CR-VANET), where CR device can detect possible idle spectrum for VANET communications and assist to timely broadcast safety-message. Given high-speed mobility of vehicles and dynamically-changing availability of channels, a novel prediction algorithm is proposed to pick out the channel with the greatest probability of availability, which can meet the quality of service (QoS) requirement of urgent communications and effectively avoid conflict with licensed users. Specifically, the spatiotemporal correlations among historical spectrum sensing data are exploited to form prior knowledge of channel availability probability, and Bayesian inference is used to derive posterior probability of channel availability. Comparing with other spectrum detection methods, the proposed algorithm has more than 8 percent detection performance improvement at false alarm probability 0.2, and thus can avoid access conflict with licensed users dramatically. Furthermore, the proposed algorithm always has larger packet reception probability (PRP) and lower transmission delay compared with conventional VANET broadcasting. Hence, the proposed algorithm can improve reliability of safety-message transmission and enhance driving safety significantly.

Homelessness and the Ethics of Information Access

Many public libraries have rules against strong body odor, bringing large amounts of luggage into the library, sleeping, and bathing in restrooms. These rules disproportionately affect library patrons who are experiencing homelessness. This article reviews recent literature that considers legal and social justice perspectives on homelessness and libraries, as well as the policies of four urban public library systems. Although these rules may be legal and are widely used, people without homes have no other access to information and thus have an even stronger need for the resources of public libraries than other members of the general public. The author concludes that blocking their access conflicts with the mission of public libraries to provide information to all.

Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder

This paper presents the algorithm and the architecture of the high-throughput motion estimation system for the H.265/HEVC encoder. The design allows the processing of [email protected] videos at the clock frequency of 400 MHz. The architecture embeds two parallel processing paths for the integer-pel and the fractional-pel motion estimation. The paths share the same memories. Access conflicts are avoided by the use of dual-port modules and register buffers for reused samples. In each clock cycle, the integer-pel and the fractional-pel path can evaluate one and four motion vectors for an 8 × 8 luma block, respectively. A separate interpolator for chroma additionally increases the throughput. The integer-pel path supports test zone search for 8 × 8 prediction blocks. The motion estimation for larger blocks is performed by the utilization of results of the 8 × 8 search. The search for rectangular PUs is performed only at the fractional-pel level and reuses partial costs computed for square PUs. As a consequence, a significant amount of computation is saved. Synthesis results show that the design can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively. The implemented algorithm is verified in the HM16 software. If [email protected] videos are encoded with the low-delay configuration, BD-PSNR and BD-rate are equal to ?0.026 dB and 1.64 %, respectively.

Dyn-ARF: a rate adaptation mechanism sensitive to the network load over 802.11 WLANs

Since the first version of the IEEE 802.11, the standard committee has included a set of transmission rates aiming to accommodate the wide variety of requirements of end-user devices and channel operating conditions. Traditionally, the sender increases the data transmission rate upon receiving various consecutive acknowledgement packets while the data transmission rate is decreased on the absence of acknowledgement packets. This error-control procedure assumes that the channel operating conditions are the main source of transmission errors and losses. However, under medium or high load conditions, transmission impairments are mainly due to channel access conflicts: collisions. Under these load conditions, reducing the data transmission based exclusively on the absence of feedback not only proves ineffective, but it actually degrades the overall network performance. In this paper, we describe a novel rate adaptation mechanism capable of mitigating the effect of collisions using the information imbedded in the received packets. Simulation results show that our proposal limits the use of the data transmission adaptation mechanism which in turn results on a significant increase of the aggregated throughput.

Design of a High-Throughput QC-LDPC Decoder With TDMP Scheduling

Low-density parity-check (LDPC) codes with turbodecoding message-passing (TDMP) scheduling can obtain good performance and high convergence rates. In addition, the min- sum (MS) algorithm can reduce the complexity. The hybrid normalized MS algorithm with TDMP scheduling is presented to achieve good performance and to lower the complexity. For a quasi-cyclic LDPC (QC-LDPC) code with a long code length, parallel degree optimization and an offset iterative sequence rule are proposed. With the proposed techniques, the data correlation problem and memory access conflicts during TDMP scheduling can be resolved so that the iteration can smoothly proceed through the reasonable division of each block row. Fabricated in the 90-nm 1-Poly 9-Metal (1P9M) CMOS process, a multimode 96000-bit irregular QC-LDPC decoder is implemented. It attains throughputs of 1.7-3.0 Gb/s and dissipates an average power of 502 mW at an operation frequency of 100 MHz and at 10 iterations. The decoder chip area is 13.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with a core area of 9.73 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .