AC Signal Source Research Articles

Design of low power RF CMOS power amplifier structure with an optimal linear gain controller for future wireless communication

A power amplifier is a two-pair terminal gadget that creates a measured reflection of the input current at the high-resistance output terminal. Which holds the output current permanently regardless of loading? The significant elements affecting the presentation of a superior power amplifier are the amount of operation, and the amount of bandwidth, output resistance, and the minimum voltage drop required at both the input and output port terminal of the power amplifier circuits. To defeat those issues, low power RF CMOS PA is proposed with an optimal linear gain controller, which is reasonable for future wireless communication broadband applications. Bandwidth, high power-added efficiency, power utilization, and linearity, are focused on the proposed design. Fundamental commitments are summed up as follows. Here, an ideal linear gain controller plays out a completely differential CS arrangement of the cascade semiconductor gate contains an inductor, which is combined between the cascade semiconductor gate and opponent cascade semiconductor sources, it enhances voltage gain and improves the linearity. The XOR- based frequency multiplier removes the passive components. A computerized pre-warping method is additionally used to remunerate the discrete force gain variations and beats the tradeoffs between power proficiency and linearity. The proposed PA implemented the 0.13-μm standard RF CMOS method. The presentation of the propounded PA is contrasted with the current PAs with performance metrics are power-added efficiency (PAE), linearity, voltage gain, and power gain. So, it is being examined with a 256-QAM WLAN 802.11ac signal source.

A 5-GHz WLAN RF CMOS Power Amplifier With a Parallel-Cascoded Configuration and an Active Feedback Linearizer

This paper presents a highly linear cascode power amplifier (PA) for 5-GHz 802.11ac (wireless local area network) WLAN applications, which is fabricated with a 0.13- $\mu \text{m}$ standard RF CMOS process. A parallel-cascoded configuration is proposed to cancel out third and fifth intermodulation distortions and third harmonic distortion (HD) due to drain–source current nonlinearity. This also reduces distortions due to drain–source and gate-source nonlinear capacitances at both common source (CS) and common gate (CG) stages. The configuration allows the amplifier linear characteristics to be robust against gate node voltage variations of CG transistors compared to previous multigated transistor linearization methods, because the CG transistors always remain in the saturation region and the nonlinearities of capacitances associated with CG transistors cancel each other under a wide range of output powers. In addition, an active feedback linearizer is applied to improve AM–AM and the power-added efficiency (PAE) at high output powers. At 5.15 GHz, the proposed PA is tested with a 256-quadrature amplitude modulation WLAN 802.11ac signal source without digital predistortions. The output powers satisfying the stringent linearity, a −35-dB error vector magnitude, are 17.8, 17.3, and 15.6 dBm with 11.5%, 10.4%, and 7.5% PAEs at 20, 40, and 80 MHz, respectively.

A Fully Integrated RF CMOS Front-End IC for Connectivity Applications

A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13- $\mu\text{m}$ bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching network satisfies the optimum matchings for a multimode PA and a shared LNA. Measurements showed a 16.2-dBm $P_{\mathrm{OUT}}$ , with a 6.7% power-added efficiency (PAE), at −34-dB error vector magnitude, with an 802.11ac signal source, with a high-power-mode WLAN PA. With a low-power-mode BT PA, it showed a 13.7-dBm $P_{\mathrm{OUT}}$ , with a 10.9% PAE, with a 2.1+EDR signal. The shared LNA has a 14.8-dB gain and a 3.6-dB noise figure. All the measurements were carried out, including integrated mode-change switches for time-division duplex operation without any digital predistortion.

A WLAN CMOS power amplifier with insensitive bias circuits

ABSTRACTA CMOS power amplifier (PA) for IEEE 802.11b/g/n/ac applications is presented, which is implemented with a 0.13‐µm standard RF CMOS process. Integrated bias circuits for the common source (CS) and common gate (CG) power transistors are proposed, which reduce the performance sensitivities of the PA according to the variations of the bias voltage and output power. Measurements show that the proposed power amplifier achieves 17.2 dBm output power with 8.1% PAE at −34 dB EVM with MCS8, 256QAM, 40 MHz, 802.11ac signal source. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2331–2334, 2016

Ultrafast active mixer using polyelectrolytic ion extractor

We report on a low voltage, straight/smooth surface, and efficient active micromixer. The mixing principle is based on alternative ion depletion-enrichment using a pair of positively charged polyelectrolytic gel electrodes (pPGEs), which face each other joined by a microchannel. This system has an external AC signal source electrically connected to the pPGEs via the respective 1 M KCl solutions and Ag/AgCl electrodes. When an electric bias is applied between the two pPGEs, anions are extracted through one of the pPGEs to create a local ion-deficient region. Simultaneously, an ion-rich area appears near the other pPGE due to an inward anionic flux. As the direction of the charge flow is periodically reversed by the AC signal source, the ion depletion-enrichment regions are alternately swapped with each other on the 'push-pull' basis. The turmoil between the pPGEs quickly mixes the solutions in the microchannel without any mechanical moving part or specially machined structures. In the proposed system, both AC frequency and current density can be easily and finely controlled so that one can quickly find the optimal conditions for a given sample. The micromixer as made showed a mixing efficiency higher than 90% for sample solutions of 1 mM Rhodamine 6G and PBS at pH 7.4 when the flow rate was under 6 mm s(-1). In addition to the solution-solution mixing, the micromixer can effectively mix suspended microparticles with solution. As a representative example, rapid and efficient lysis of human red blood cells was demonstrated allowing minimal damage of the white blood cells.

Hysteretic behavior of signal amplification using SNS junctions

A superconductor–normal metal–superconductor junction (SNS junction) has a nonlinear current–voltage characteristic (CVC) that may exhibit the low-voltage negative differential resistance (LVNDR) effect. Taking advantage of this remarkable effect it may be possible to associate a SNS junction to conventional electronic circuits in order to design devices such as oscillators, amplifiers and mixers. This work simulates the output signal of an amplifier device, which is essentially a SNS junction connected with an adjustable DC voltage supplier, and an AC signal source, which could be a SNS junction as well. Sometimes the LVNDR effect is hidden under a low-voltage hysteresis on the CVC because the experiment has been performed in a current-bias measuring setup. We focus on the question of this hysteretic behavior and discuss the performance of the proposed device with and without hysteresis.

Simulations of signal amplification and oscillations using a SNS junction

A Superconducting - Nonnal metal - Superconducting junction (SNS junction) may exhibit a Low Voltage Negative Differential Resistance (LVNDR) effect over part of its Current Voltage Characteristic (CVC). As the LVNDR effect is stable against a bias voltage at this CVC range, it should be possible to combine a SNS junction with conventional electronic circuits to obtain electronic devices such as mixers, amplifiers and oscillators. Making use of this remarkable effect, we show that an amplifier may be feasible by assembling a simple voltage divider made up of a SNS junction in series with a resistor. The amplifier circuit includes an adjustable DC voltage supply (the bias voltage) and an AC signal source with a given voltage. The SNS junction is connected in series with a resistor R. Choosing values of the load resistance R approximately equal to the module of the negative differential resistance (dV/dI), at the bias voltage, we may obtain large gains in this amplifier device. In order to get an oscillator, the SNS junction should be connected to a RLC tank circuit with a bias voltage adjusted in the range of the LVNDR region of its CVC. A power output of the order of one microwatt may be easily obtained.

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Frequency Multiplication By A P-I-N Diode When Driven Into Avalanche Breakdown

An investigation of frequency multiplication using a step-recovery diode (SRD) driven into avalanche is presented. This mode of operation, which is called the breakdown mode, consists of a reverse-biased p-n junction, SRD, or IMPATT diode driven into reverse by an ac signal source. As the diode voltage passes from reverse bias to reverse and avalanche, the state of the diode switches quickfy from a depletion-layer capacitance to an avalanche inductance; hence the production of strong harmonics. A theoretical analysis and experimental investigation of a coaxial/waveguide 2-6-GHz frequency multiplier using HP5082-0320 step-recovery diodes, [R/sub s/ = 0.75 Omega, C/sub d/(-6/sub v/) = 1.0 pF] shows that the breakdown-mode frequency multiplier has a higher conversion efficiency than the conventional multipuer. A measured conversion efficiency of 73 percent was achieved while the same circuit configuration produced 52 percent for the same diode used as a charge-storage multiplier under optimum forward-drive and tuning conditions. Also the theory developed in this paper indicates a maximum possible conversion efficiency of 80 percent for the breakdown-mode multiplier, which corresponds closely with the measured results, and a maximum theoretical efficiency for a forward driven diode of 64 percent. The performance of an FM microwave system was monitored using the multiplier as a LO in which a baseband SNR of 59 dB was recorded.