AC Noise Research Articles

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

CMOS Noise Analysis and Simulation From Low Frequency and Baseband to RF and Millimeter Wave

Generic guidelines for noise simulation of CMOS integrated circuits and advanced noise signal integrity analyses, were addressed in this work. The provided noise simulation guidelines are referring to a wide application spectrum, from baseband designs to high frequency RF/mmWave applications. Linear, periodic state and non-linear circuits, were used to categorize the noise simulation guidelines to the respective topology in which they can be applied. In addition, thermal, flicker and gate induced noise, were addressed, and classified with respect to the application field. Three test case vehicles were designed, each vehicle corresponds to a linear, periodic state or non-linear circuit type. As a linear vehicle, an Operational Transconductance Amplifier (OTA) was designed, as a periodic state vehicle, a Voltage Controlled Oscillator (VCO) was designed while as a non-linear vehicle, a DC-to-DC Boost Converter was designed. Small-signal and large-signal noise analyses were benchmarked in terms of simulation time, compatibility and obtained accuracy. As small-signal analyses, AC noise, PNOISE and ENVLP analyses were performed, whereas as large-signal analyses, direct time domain (TRAN), PSS and QPSS analyses were performed in the respective topologies. Furthermore, using as a victim the VCO test case circuit, noise interference due to mutual coupling (mixing interference) was thoroughly addressed and simulation compatibility check was presented. Finally, noise simulation guidelines were efficiently summarized and categorized with respect to the circuit type and the application field.

Integrated CM Inductor for Both DC and AC Noise Attenuation in DC-Fed Motor Drive Systems

Using passive electromagnetic interference (EMI) filter to suppress the common mode (CM) noises on the dc and ac side of motor drive systems is a common filtering method. Shrinking the volume of CM inductors is the key to the miniaturization of EMI filters. In order to reduce the volume, this article proposes a new method to integrate the dc and ac CM inductors by magnetic coupling. The principle of the filter and the design constraints of coupled CM inductors are analyzed. The filter volume reduction advantage gained by using the proposed method is illustrated. A model is built to describe the relationship between the coupling coefficient and filtering performance. Finally, the procedures for design of coupled inductors are addressed and the results are verified by experiments. In the comparative case study, the volume of coupled inductor is 90% of that of discrete inductor.

A PVT tolerant latch in a 90-nm CMOS and performances under AC noise

ABSTRACT Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Multiplexer (mux) latch is one of the key components for serializer interface to admit communication at Gbps. This work describes the working of a 2:1 mux-latch coupled to a power delivery network (PDN) and a CPU core drawing abrupt current. In comparison to conventional designs, multiplexer and latch operate at the same time, which is quite different because enable inputs are imperative to start latch operation. An analytical model is also derived to understand power delay trade-off and to choose gate sizes to obtain a comparable delay without increasing power. The average power and delay in post-layout are 257.7 μW and 35 ps, respectively, in a 90-nm CMOS, power supply voltage (Vdd) of 1.1 V and a clock switching at 6.25 GHz. However, a 117OC change in temperature at distinct corner allows average power to vary between 32.8 and 64 μW. The corresponding variation is 135–183.7 μW as Vdd switches from 0.75 to 1.1 V. In addition to so, delay changes between 5-14 ps and 3–12 ps for the given change in temperature and Vdd, respectively. Nonetheless, the effective supply voltage VP oscillates with time as the CPU core draws abrupt current. The delay values due to AC noise are found to be different than VP having no noise and the corresponding jitter changes linearly as a function of noise.

Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current

A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0[Formula: see text]A) to 10 or 30[Formula: see text]A or else 50[Formula: see text]A in 10[Formula: see text]ns. Simulated in a 0.09-[Formula: see text]m CMOS process and power supply voltage ([Formula: see text]) of 1.1[Formula: see text]V, the proposed circuit in post-layout can operate from 435.5[Formula: see text]ps to 152.2[Formula: see text]ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5[Formula: see text]ps for NN and SS process corner, respectively, following a [Formula: see text]C change in temperature. But an abrupt high current [Formula: see text] pumped into the chip causes the voltage ([Formula: see text]) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp [Formula: see text] of 0–50[Formula: see text]A in 10[Formula: see text]ns for the two vector CBA happens to be around 5.0 and 4.4[Formula: see text]ps, respectively. The current ramp also generates power supply noise of 0.468[Formula: see text]V occurring close to the silicon chip. This, in turn, corresponds to a [Formula: see text] of 0.642[Formula: see text]V near the die, appearing to be much less than the required [Formula: see text] of 1.1[Formula: see text]V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642[Formula: see text]V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage.

Scanning Nitrogen Vacancy Magnetometry: A Quantum Technology for Device Failure Analysis

Abstract This article describes the basic measurement physics of scanning nitrogen vacancy (NV) microscopy and the various ways it can be used in semiconductor device failure analysis. Scanning NV microscopy can measure topography as well as magnetic fields, local current density, ac noise, and local temperature variations.

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors

A Low-power and low-noise digital pixel sensor (DPS) is presented in this paper. To design and analyze the random noise (RN) of the developed DPS, especially, we utilize a novel simulationmethod called transient-based AC noise simulation (TBAS) which can effectively help to estimate the noise components of the lowpowered single-slope (SS) analog-to-digital converter (ADC). Based on this noise analysis, the high performance DPS has been successfully designed and demonstrated.

Impact of the Absorber-Coupling Design for Transition-Edge-Sensor X-Ray Calorimeters

Transition Edge Sensors (TESs) are the selected technology for future spaceborne X-ray observatories, such as Athena, Lynx, and HUBS. These missions demand thousands of pixels to be operated simultaneously with high energy-resolving power. To reach these demanding requirements, every aspect of the TES design has to be optimized. Here we present the experimental results of tests on different devices where the coupling between the x-ray absorber and the TES sensor is varied. In particular, we look at the effects of the diameter of the coupling stems and the distance between the stems and the TES bilayer. Based on measurements of the AC complex impedance and noise, we observe a reduction in the excess noise as the spacing between the absorber stem and the bilayer is decreased. We identify the origin of this excess noise to be internal thermal fluctuation noise between the absorber stem and the bilayer. Additionally, we see an impact of the coupling on the superconducting transition in the appearance of kinks. Our observations show that these unwanted structures in the transition shape can be avoided with careful design of the coupling geometry. Also the stem diameter appears to have a significant impact on the smoothness of the TES transition. This observation is still poorly understood, but is of great importance for both AC and DC biased TESs.

Electronic noise of warm electrons in semiconductors from first principles

The ab-initio theory of low-field electronic transport properties such as carrier mobility in semiconductors is well-established. However, an equivalent treatment of electronic fluctuations about a non-equilibrium steady state, which are readily probed experimentally, remains less explored. Here, we report a first-principles theory of electronic noise for warm electrons in semiconductors. In contrast with typical numerical methods used for electronic noise, no adjustable parameters are required in the present formalism, with the electronic band structure and scattering rates calculated from first-principles. We demonstrate the utility of our approach by applying it to GaAs and show that spectral features in AC transport properties and noise originate from the disparate time scales of momentum and energy relaxation, despite the dominance of optical phonon scattering. Our formalism enables a parameter-free approach to probe the microscopic transport processes that give rise to electronic noise in semiconductors.

Finding and Eliminating Noise and Interference in a Test Stand for Josephson Digital Chips

Sources of noise and interference in a test stand for Josephson digital integrated circuits have been identified and eliminated using a novel measurement technique. The digital output of the chip was fed into a spectrum analyzer while the output pattern was 1010. The DC bias was set at the boundary between correct and incorrect operation, a 50% bit error rate. Small AC noise currents on the bias made large changes in the bit error rate. This converted noise currents to amplitude modulation sidebands of the data pattern at half of the logic clock frequency, which was 625 MHz. AC currents were injected at 454 Hz to produce AM sidebands at 625 MHz ± 454 Hz. The sideband power was directly proportional to calibration tone power over the range 50 nA to 10 μA. Noise currents on the DC bias as small as 100 nA were clearly identified at 120 Hz. The largest noise currents in the test setup were found near 40 MHz. Their spectrum of evenly spaced tones indicated that the source was a switching power supply. When an idle relay controller was turned off, the noise tones immediately disappeared from the spectrum analyzer display, confirming the source of interference. This new and easy to use technique exploited bit error rate modulation to up convert AC noise currents from low frequencies to the range 625-675 MHz. The location of the noise currents was unambiguous, since only a 60 Hz noise current on the chip could produce an AM sideband at 625 MHz plus 60 Hz.

Outdoor Investigation of the Corona Characteristics and Audible Noise of a Hybrid AC/DC Overhead Line

Electric utilities are looking for novel methods to increase the transmission capacity of existing transmission lines. The conversion of conventional AC towers to hybrid AC/DC lines allows for significantly more power and reduces the need for new rights of way. Still, due to the fixed geometry, there will be coupling effects between the AC and DC systems. Corona effects, such as audible noise, which are crucial for public acceptance, must be controlled to obtain crucial public acceptance. An outdoor test setup is used to investigate the corona audible noise and partial discharges of parallel AC and DC bundles. The effect of a DC bias on the AC corona as well as an AC ripple on DC corona are studied for varying surface gradients and weather conditions. The AC and DC audible noise clearly increased for most cases of a DC bias or AC ripple, respectively. The relative increase was found higher if the conductor was only slightly above corona as it happens in dry conditions with light pollution. Still, the highest level of AC audible noise was observed during wet weather and for DC during dry conditions.

Improving the signal-to-noise ratio for heat-assisted magnetic recording by optimizing a high/low Tc bilayer structure

We optimize the recording medium for heat-assisted magnetic recording by using a high/low Tc bilayer structure to reduce AC and DC noise. Compared to a former work, small Gilbert damping α=0.02 is considered for the FePt-like hard magnetic material. Atomistic simulations are performed for a cylindrical recording grain with diameter d=5nm and height h=8nm. Different soft magnetic material compositions are tested, and the amount of hard and soft magnetic material is optimized. The results show that for a soft magnetic material with αSM=0.1 and Jij,SM=7.72×10−21J/link, a composition with 50% hard and 50% soft magnetic material leads to the best results. Additionally, we analyze how much areal density can be improved by using the optimized bilayer structure compared to the pure hard magnetic recording material. It turns out that the optimized bilayer design allows an areal density that is 1Tb/in.2 higher than that of the pure hard magnetic material while obtaining the same signal-to-noise ratio.

Noise reduction in near infrared-based glucose concentration measurement sensor

This paper describes the method of measuring glucose concentrations in solution using near infrared light (NIR) and photodiode sensor. A sensitive and accurate non invasive blood glucose level sensor is our main concern in designing this device. The sensor consists of a transimpedance amplifier, a notch filter and a low pass filter to reduce high frequency noise and 50 Hertz noise from the power line induction. Light Emitting Diode (LED) with 1450 nm wavelength is used as a light source and a photodiode is used as a sensor to sense this wavelength. The NIR light received by the photodiode after passing glucose solution is converted to voltage signal and filtered to determine the output voltage. The measurement results show that the filters reduced the AC voltage or noise signal under 100 mV and the DC voltage tended to decrease as glucose concentration increase until 700 mg/dL.

Electrical tree growth and partial discharge in epoxy resin under combined AC and DC voltage waveforms

The effect of DC bias on electrical tree growth and partial discharge (PD) characteristics in epoxy resin (Araldite LY® 5052/Aradur® HY 5052 supplied by Huntsman) is investigated using three waveforms: AC, AC with positive DC bias, and AC with negative DC bias. Needle-plane samples are used. Tree growth is shown to be accelerated by the combined effect of DC and 50 Hz AC, beyond the AC growth rate. Positive and negative DC biased tests result in 62% and 54% reductions in average time to breakdown, respectively. Different tree structures and stages of development are associated with different partial discharge characteristics, with thick dark tree branches associated with high PD magnitudes, whereas fine tree channel growth is linked with PD magnitudes below 1 pC. AC tests showed five distinct stages of tree growth compared to four stages seen in DC biased tests. In particular, trees growing in the ‘reverse direction’ from the planar to the point electrode, which is observed in the latter stages of AC tests, is not seen in the DC biased tests. It is concluded that for composite voltages, the AC component is the essential driver of tree growth but the DC component can accelerate propagation. AC noise may therefore compromise the reliability of insulation in HVDC networks.

Optimal Design of a Band Pass Filter and an Algorithm for Series Arc Detection

Detection and analysis of series arcs is significantly meaningful for preventing arc-caused electrical fires in advance. However, the improvement of arc detection sensitivity and the discrimination of arc conditions are still challenges when developing an arc fault detector. In this paper, arc signals in various loads with three major incomplete connection states were detected and further analyzed using the discrete wavelet transform. It was verified that the db13 was the optimal mother wavelet to analyze the arc pulses and the decomposed signals in the detail components of D5, D6, D7, and D8 were related with arc phenomena. Therefore, a band pass filter with a frequency from 2.4 to 39 kHz was designed, which can extract arc signals while eliminating the AC mains current and noise generated in loads. By investigating the arc signal energy as well as the arc pulse counts that were important parameters of arc occurrence, an arc diagnosis algorithm was developed based on LabVIEW program for electrical fire prevention.

Abstract 244: ECG Recording Errors Prevalence in a Hospital Setting

Background: Electrocardiographic recording can have many potential errors due to erroneous recording which may impact their proper interpretation and patient care. OBJECTIVE: To assess the prevalence of reported ECG errors in a university hospital database with a mix of inpatient and outpatient electrocardiograms (ECG). Methods: The 1212 ECGs performed during one month were downloaded and individually analyzed for reported errors and artifacts. There were 309 (25.5%) outpatient ECGs and 903 (74.5%) inpatient or emergency department ECGs. The types of errors are reported as absolute numbers and as percentages of the total errors. Results: Among 1212 ECGs analyzed, 71 ECGs (5.9%) contained error or artifact statements. Among those, 12 ECGs (16.9%) were precordial lead misplacements. There were 2 ECGs (2.8%) with limb lead reversals. A total of 57 ECGs (80.3%) contained baseline artifacts; 12 ECGs (16.9%) had AC noise artifacts, and 45 ECGs (63.3%) had baseline wander artifacts. Out of the total ECGs with reported errors, 60 ECGs (84.5%) were performed in the inpatient or emergency department setting, while 11 ECGs (15.5%) were performed in the outpatient setting. Discussion: Electrocardiography remains the cornerstone of early diagnosis and treatment of cardiac disease in the inpatient and outpatient setting. ECG recording artifacts have been reported with variable frequency, with inpatient recordings likely suffering greater errors, depending on the acuity of the situation. We observed that in the outpatient setting, there was 3.6% (11/309) prevalence of recording error, while in the inpatient and emergency department setting there was 6.6% (60/903) prevalence of ECG recording errors. Despite the overall small percentages, this is an alarming problem, especially with regards to inpatient ECGs when the results often prompt critical treatment decisions. The reason for the discrepancy between inpatient and outpatient ECG errors is not clear. Potential causes may include the intensity of the situation with compromise of proper lead placement, such as use of Mason-Likar configuration or placing leads above the left breast in female patients or unavailability of proper recording surfaces as in trauma or burn patients, but may also be caused by the lack of availability of adequately trained staff especially in the after-hour situations. Adequate training of staff to perform proper ECGs, and creation of robust electrocardiographic interpretation algorithms to recognize more recording errors on-screen before printing is called for.

SNR improvement by variation of recording and media parameters for a HAMR exchange coupled composite media

An exchange coupled composite media structure proposed previously seems to address both the issue of Tc variation in FePt as well as poor SNR/User Density during the HAMR process. Here we examine a thinner 3-6 nm structure that is likely easier to fabricate than the previous 13.5 nm thick structure. We find that increasing the damping within the write (superparamagnetic) layer and introducing intergranular exchange within the grains in the write layer are both successful approaches to improve the recorded SNR. Ensemble waveform analysis that allows the breakdown of the total SNR into transition SNR (due to AC noise) and remanence SNR (due to DC noise) helps identify the leading causes for this SNR improvement. Further studies indicate that varying the peak heat spot temperature in the HAMR write process is also a successful approach for improving the recorded SNR. This lends credence to the idea that a thinner composite media may still be used successfully to realize significant enhancements of SNR and the corresponding user density.

Noise Reduction Based on an Fe−Rh Interlayer in Exchange-Coupled Heat-Assisted Recording Media

High storage density and high data rate are two of the most desired properties of modern hard disk drives. Heat-assisted magnetic recording (HAMR) is believed to achieve both. Recording media, consisting of exchange coupled grains with a high and a low $T_{\mathrm{C}}$ part, were shown to have low DC noise, but increased AC noise, compared to hard magnetic single phase grains, like FePt [1]. In this work we extensively investigate the influence of an FeRh interlayer on the magnetic noise in exchange coupled grains. We find an optimal grain design that reduces the jitter in down-track direction by up to 30 % and in off-track direction by up to 50 %, depending on the head velocity, compared to the same structures without FeRh. Further, the mechanisms causing this jitter reduction are demonstrated. Additionally, we show that for ultrashort heat pulses and low write temperatures the switching time distribution of the analyzed grain structure is reduced by a factor of four, compared to the same structure without FeRh layer. This feature could be interesting for HAMR with a pulsed laser spot and could resume the discussion about this HAMR technique.

Basic noise mechanisms of heat-assisted-magnetic recording

Heat-assisted magnetic recording (HAMR) is expected to be a key technology to significantly increase the areal storage density of magnetic recording devices. At high temperatures, thermally induced noise becomes a major problem, which must be overcome in order to reliably write magnetic bits with narrow transitions. We propose an elementary model based on the effective recording time window (ERTW) to compute the switching probability of bits during HAMR. With few assumptions, this analytical model allows to gain deeper insights into basic noise mechanisms, like AC and DC noise. Finally, we discuss strategies to reduce noise and to increase the areal storage density of both bit-patterned and granular media.