4K Ultra High Definition Video Research Articles

Development of Transmitter and Receiver With Set Partitioning 64APSK Coded Modulation Designed on Basis of Channel Capacity

In this paper, we present a prototype transmitter and receiver with set partitioning (SP)-64 amplitude and phase shift keying (APSK) coded modulation we developed for expanding satellite transmission capacity. SP-multi-level coded modulation is a transmission scheme that can improve noise immunity by properly combining a modulation scheme, bit allocation, and error-correction codes. We designed SP-64APSK coded modulation on the basis of channel capacity for expanding satellite transmission capacity. We confirmed that it has higher robustness to additive white Gaussian noise (AWGN) than DVB-S2X’s 64APSK modulation with Gray mapping through computer simulation. We also developed a prototype transmitter and receiver to implement our SP-64APSK coded modulation and evaluated its transmission performances in an AWGN channel and in a non-linear channel simulating 12-GHz-band satellite transponder characteristics. We describe the method of designing our SP-64APSK coded modulation through computer simulation, the modulation/demodulation process, and transmission performances of the prototype transmitter and receiver. We also indicate that 8K ultra-high definition television (UHDTV) with an encoded bit rate of 150 Mbps can be transmitted using the prototype within 34.5 MHz, which is the bandwidth of a single transponder for satellite broadcasting in Japan.

Topographic Surveying using Low-Cost Amateur Drones & 4K Ultra-High-Definition Videos

These days, the science of photogrammetry is frequently used in a wide range of applications, including engineering geology, medication, security, navigation, and topographic surveying works. Drones have gradually become an effectual and frequent technique for obtaining a number of photogrammetric products, such as ortho-mosaics, Digital Elevation Model (DEM), and land detailed topographic maps. This paper investigates the possibility of employing low-cost amateur drones with 4K Ultra-High-Definition (UHD) video for topographic surveying works and creating DEM's. DJI Mavic 2 PRO drone with Hasselblad L1D-20C 20 MP camera has been used for covering an expected gas & oil pipeline route in the South of Libya with length of nearly 15 km and width of 200 m. 60 well-distributed high-quality 3D ground points, divided as 30 Ground Control Points (GCP's) and 30 check points, have been used for more stable and robust photogrammetric processing and for reliable evaluation, respectively. The camera has been calibrated twice, before and after executing the flight mission for trustworthy Interior Orientation Elements (IOE's). The recorded video has been split into smaller videos based on the capturing time of the required frames, and the small videos have been extracted to individual UHD photos using Matlab image tools. Leica Photogrammetric Suite (LPS) software has been used for all processing steps, except the automatic filtration of the generated tie points, which has been carried out using self-developed Matlab algorithm for epipolar geometry and 2D transformation based filters. Results show that DEM's with quality of nearly 1.2 to 2 decimeter in plane and elevation, respectively can be obtained using DJI Mavic 2 PRO drone, 4K UHD video taken by Hasselblad L1D-20C 20 MP camera, pixel ground footprint of 8 cm, and flight height of 350 m. This level of accuracy is appropriate for many engineering applications, such as initial-planning projects stretched on huge areas, urban development plans, GIS data collection, inventory of earth works materials, and 3D modeling. The obtained quality of the generated DEM depends on the flight height and the camera quality, IOE's, and resolution. Tests show that using 4K UHD video for photogrammetric applications can provide UHD extracted frames, similar to that captured singly, especially with fit flight speed and camera settings, namely: ISO sensitivity, shatter speed, and aperture size. Also, using video facilitates the aerial photography process, overcoming the difficulties of determining the suitable capturing time and location of individual photos in site. The other advantage is the ability of taking alternative frames if the selected images are not suitable for photogrammetric works in terms of tilting and blurring. The opportunity of changing the overlapping rates across the route is another important advantage of using video, especially for curvy routes. Moreover, using different groups of overlapped images for the same route helps for creating different DEM's for the same area, resulting more precise and dense topographic surveying works.

DVL2021: An ultra high definition video dataset for perceptual quality study

This paper describes an ultra high definition (UHD) video dataset named DVL2021 for the perceptual study of video quality assessment (VQA). To our knowledge, DVL2021 is the first authentically distorted 4K (3840 × 2160) UHD video quality dataset. The dataset contains 206 versatile 4K UHD video sequences, which are all collected in in-the-wild scenarios. Each sequence is captured at 50 frames per second (fps), stored in raw 10-bit 4:2:0 YUV format, and has a duration of 10 s. Following the subjective evaluation method of TV image quality granted by ITU-R BT.500-13, 32 unique participants take part in the manual annotation process, whose ages are from teenage to sixties (32.7 years old on average). DVL2021 has the following merits: (1) enormous variety of video contents, (2) captured by different types of cameras, (3) complex types and multiple levels of authentic distortion, (4) broadly distributed temporal/spatial information, and (5) a wide spectrum of mean opinion scores (MOS) distribution. Furthermore, we conduct a benchmark experiment by evaluating several mainstream VQA methods on DVL2021. The baseline results are higher than 0.75 in Spearman’s rank order correlation coefficient (SROCC) metric. Our study provides a basis for the UHD VQA problem. DVL2021 is publicly available at https://github.com/GZHU-DVL/DVL2021.

Development of an 8K UHDTV Wireless Camera Using Millimeter-Wave Bands

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Wireless cameras enable dynamic shooting and have become indispensable in television program production for sporting events and music concerts. Japan Broadcasting Corporation (NHK) has researched and developed an 8K ultrahigh-definition television (UHDTV) wireless camera using millimeter waves that can transmit an 8K signal with low latency and high quality. We have prototyped a compact transmitter using the 42-GHz band and developed an 8K UHDTV wireless camera by combining this transmitter with a portable 8K UHDTV video encoder. In this study, we introduce a prototype 8K UHDTV wireless camera system using millimeter waves and report the results of laboratory and field wireless transmission experiments</i> .

48‐Gbit/s 8K video‐transmission using resonant tunnelling diodes in 300‐GHz band

The authors report on a real-time 48-Gbit/s terahertz band wireless communication experiment employing a pair of resonant tunnelling diodes at the receiver and uni-travelling carrier photodiodes at the transmitter. The wireless transmission of uncompressed full-resolution 8K ultra high-definition television video signal is successfully demonstrated in the 300-GHz band for the first time.

Impact of packet loss on 4K UHD video for portable devices

Ultra High Definition (UHD) video streaming to portable devices has become topical. Two standardized codecs are current, H.264/Advanced Video Coding (AVC) and the more recent High Efficiency Video Coding (HEVC). This paper compares the two codecs’ robustness to packet loss, after making allowances for relative coding gain. A significant finding from the comparison is that the H.264/AVC codec is less impacted by packet loss than HEVC, despite their differing coding efficiencies and including at low levels of packet loss. The results will be especially relevant to those designing portable devices with 4K UHD video display capability, allowing them to estimate the level of error concealment necessary. The paper also includes the results of HEVC compressed UHD video streaming over an IEEE 802.11ad wireless link operating at 60 GHz as a pointer to future performance in an error-prone channel.

Implementing 8K Vision Mixer for Cloud-Based Production System

We are developing an IP-based program production system for 8K ultrahigh-definition television (UHDTV). SMPTE ST 2110-20, which is the standard for transporting video over IP network, covers 8K transmission. However, the required bandwidth to transport an uncompressed 8K image (YCbCr 4:2:2, 10 bits, and 60 frames/s) is about 40 Gbits/s, so devices must use a high-bandwidth interface such as 100 Gigabit Ethernet (GbE). Also, devices for processing a single 8K stream require far more processing power than 2K and 4K production devices. To transport 8K images on multiple low-bandwidth interfaces and processes with general-purpose CPUs, our system divides a high-resolution image into multiple low-resolution subpictures and transports each subpicture as a SMPTE ST 2110-20 flow. This system has three advantages. First, this method enables us to use affordable low-bandwidth interfaces and CPUs to build a program production system for the high-resolution image. Second, as production devices for low resolution can be used as part of a production system for high resolution with this method, broadcasters can upgrade their system instead of replacing it. Finally, this method enables us to operate a production facility more efficiently and flexibly. As processing 2K images does not require high performance, production processes can be performed without high CPU usage. We can implement a software production system and run it on generic servers to enable us to deploy and use resources for program production on demand.

Development of Full-Featured 8K Recorder

NHK has been researching a full-featured 8K ultrahigh-definition television system with a high frame rate of 120 Hz (8K/120 Hz) for future broadcasting. We have developed 8K encoder and decoder boards that support a popular video codec widely used in nonlinear editing (NLE). Installing these boards into our prototype 8K recorder realizes realtime 8K/120 Hz compression and decompression. The recorder can store 60 min of a compressed stream in a single removable memory with solid-state drives. We constructed an 8K post-production system and performed an 8K/120 Hz editing experiment with the recorded content. In the system, an NLE machine was connected to Redundant Arrays of Inexpensive Disks (RAID) devices through a high-speed interface appropriate for transferring a compressed 8K/120 Hz source. Common NLE software was used that works with 4K/60 Hz video reproduced from original 8K files by applying the resolution scalable decoding function of the codec, and the edited scenes were finally rendered at 8K/120 Hz system. With the 8K/120 Hz NLE system, approximately 350 min of footage was handled, and more than 100 min of content was mastered. To perform an 8K full-frame preview at editing sites, we also developed a peripheral playout module that incorporates a decoder for the recording codec and 8K/60 Hz output interface (quad-link 12G-SDI) in a single Peripheral Component Interconnect express (PCIe) card. By driving two modules in parallel, we achieved realtime 8K/120 Hz playout in a workstation. Furthermore, a compact removable memory with a nonvolatile memory express interface for offering good connectivity with editing systems was prototyped. These achievements can provide cost-efficient editing and playout, which makes 8K/120 Hz post-production more convenient than ever before.

A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K

A professional-image-quality video encoder LSI for broadcasting and content distribution has been developed with single-chip 4K 60-fps 4:2:2 high-efficiency video coding (HEVC) encoding capability and 8K ultrahigh definition television scalability. Edge-based intramode pruning and statistically adaptive multiblock-size motion estimation (ME) efficiently reduce HEVC’s high computational complexity for real-time processing, while a deeply centralized-mode decision framework maintains high compression performance. Internal reference image caches with 797-Gb/s image feed capability support the 768-GOPS ME computation of distributed motion vector search. Interchip pictures and data exchange features with high-speed data buses are also used for multichip 8K encoding configuration. A subjective evaluation showed that the proposed encoder LSI maintained the same visual quality as an encoder LSI complying with the previous standard while reducing bit rate by 40%. The chip was designed and fabricated in a 28-nm CMOS technology and used to build industry-leading 4K and 8K broadcasting systems.

A 100 Gbit/sec Interface for 4K/8K UHDTV Signals

A 100 Gbit/sec realtime interface has been developed specifically to transmit 4K and 8K ultrahigh-definition television (UHDTV) image formats. This 100 Gbit/sec interface can carry 8K/50p-60p/4:4:4/12-bit or 8K/100p-120p/4:2:2/10-bit image formats. The dc balance and clock recovery were secured by adopting the 8b/10b coding. A transmission distance of 2 km, the same as those of the HD/3G-SDI optical interfaces, was achieved by adopting the 1.3 $\mu \text{m}$ Quad Small Form-factor Pluggable 28 (QSFP28) optical module. The QSFP optical module has evolved and treats the data as $4\times28$ Gbits/sec. This 100 Gbit/sec interface can be the next-generation realtime interface that can cover all the 4K and 8K signal formats defined by SMPTE ST 2048–1 and ST 2036–1 as well as ST 274 and ST 296. It also maintains backward compatibility because its I/O supports HD/3G-SDI.

Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding

An approximate kernel for the discrete cosine transform (DCT) of length 4 is derived from the 4-point DCT defined by the High Efficiency Video Coding (HEVC) standard and used for the computation of DCT and inverse DCT (IDCT) of power-of-two lengths. There are two reasons for considering the DCT of length 4 as the basic module. First, it allows computation of DCTs of lengths 4, 8, 16, and 32 prescribed by the HEVC. Second, the DCTs generated by the 4-point DCT not only involve lower complexity, but also offer better compression performance. Fully parallel and area-constrained architectures for the proposed approximate DCT are proposed to have flexible tradeoff between the area and time complexities. In addition, a reconfigurable architecture is proposed where an 8-point DCT can be used in place of a pair of 4-point DCTs. Using the same reconfiguration scheme, a 32-point DCT could be configured for parallel computation of two 16-point DCTs or four 8-point DCTs or eight 4-point DCTs. The proposed reconfigurable design can support real-time coding for high-definition video sequences in the 8k ultrahigh-definition television format ( $7680\times 4320$ at 30 frames/s). A unified forward and inverse transform architecture is also proposed where the hardware complexity is reduced by sharing hardware between the DCT and IDCT computations. The proposed approximation has nearly the same arithmetic complexity and hardware requirement as those of recently proposed related methods, but involves significantly less error energy and offers better peak signal-to-noise ratio than the others when DCTs of length more than 8 are used. A detailed comparison of the complexity, energy efficiency, and compression performance of different DCT approximation schemes for video coding is also presented. It is shown that the proposed approximation provides a better compressed-image quality than other approximate DCTs. The proposed method can perform HEVC-compliant video coding with marginal degradation of video quality and a slight increase the in bit rate, with a fraction of computational complexity of the latter.

Development of an 8K full-resolution single-chip color image acquisition system

We have been researching compact 8K ultra-high definition television (UHDTV) camera systems for practical use. In this paper, we describe the world's first 8K &#x201C;full-resolution&#x201D; single-chip image acquisition system. This system can obtain an 8K full-resolution image at 60 frames-per-second, which has 33 megapixels for each color, using a 133-megapixel color CMOS image sensor. To reduce the size of the camera head, the signal processing is implemented in the separated camera control unit (CCU). The signal from the camera head to the CCU is transmitted using four 25-Gbps optical signals through one single-mode optical fiber by wavelength division multiplexing (WDM) technology. The signal processing unit can process all the 133-megapixel image data in real-time and can output an 8K video signal that is compliant with the ARIB STD-B58 and ITU-R BT. 2077 standards (U-SDI).

Celebrating the Launch of 8K/4K UHDTV Satellite Broadcasting and Progress on Full-Featured 8K UHDTV in Japan

NHK started the world's first test satellite broadcasting of 8K/4K ultra-highdefinition television (UHDTV), called Super Hi-Vision (SHV), on August 1, 2016. Coverage of the Rio Olympic Games and many fascinating 8K and 4K programs were broadcasted to 8K prototype receivers installed at all of NHK's local stations in Japan. This paper describes the SHV test broadcast system, especially the program play-out and transmission system and the 8K/4K receivers. In addition, it describes the progress made so far in developing a full-featured 8K system with a 120-Hz frame frequency.

ADT-Based UHDTV Transmission for the Existing ATSC Terrestrial DTV Broadcasting

In this brief, we propose an augmented data transmission (ADT)-based ultrahigh definition (UHD) television transmission system for the existing advanced television systems committee terrestrial digital television (DTV) broadcasting. The proposed system can support a rate of 12 Mb/s using a moving pictures expert group-2 (MPEG-2)-based DTV signal and a rate of 12.5 Mb/s using High Efficiency Video Coding (HEVC)-based DTV and ADT signals. By combining properly an MPEG-2-based DTV signal, an HEVC-based DTV signal and an HEVC-based ADT signal, 4K (3840 × 2160 ) UHD video can be served while providing backward-compatible high-definition video service.

HEVC 부호기를 위한 효율적인 SAO의 저면적 하드웨어 설계

ABSTRACT This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC 0.13μm CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e.g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 × 4,320 at 30 fps) in real time.

Exploiting Coarse-grained Parallelism in Multi-transform Architectures for H.264/AVC High Profile Codecs

A parallel Multi-Transform Architecture (MTA) for the computation of the 2-D transforms adopted in modern digital video standards is proposed in this paper. This hardware structure can be dynamically configured to efficiently compute either one transform of size N × N ,o rk different transforms of size N k × N k in simultaneous, where N ∈ N and k = 2 i with i = 1, ..., lo g2 N − 1. The advanta ges offered by the proposed parallel architecture were assessed by implementing in a Xilinx Virtex-7 FPGA a proof-of-concept t ransform core compliant with the High Profiles of the H.264/AVC standard. The obtained results show that such processing structu re is capable of achieving real-time operation for video sequences in the 8k Ultra High Definition Television (UHDTV) format (7680 × 4320 @ 30 fps). In addition, these results also demonstrate that the proposed parallel MTA allows to, at least, double both the throughput and the hardware efficiency of the implemented transform cores, when compared to the original design of the archi tecture. c