8-bit Data Research Articles

High Resolution Frequency Measurement Techniques for Relaxation Oscillator Based Capacitive Sensors

This work presents high resolution and adaptable frequency measurement techniques for relaxation oscillator based capacitive sensors. The techniques rely on extremely simple hardware such as a 1-bit coarse voltage quantizer to generate a 1-bit data stream and subsequently determine frequencies with resolutions greater than 20 bits from the 1-bit data stream. The proposed readouts are based on two types of 1-bit hardware approaches with Nyquist sampling in one approach and oversampling in the other. The first approach employs a Nyquist rate sampled 1-bit comparator while the second approach relies on an oversampled 1-bit quantizer based delta-sigma modulator (DSM) as a hardware to generate the bit stream. High resolution frequency is estimated from the 1-bit data stream using parametric, non-parametric and compressed sensing approaches. We provide detailed study and measurement results comparing the performance of the proposed techniques for test inputs with different frequencies and amplitudes and multiple signal shapes including sine, square, triangular and sawtooth. We show that the 1-bit comparator along with the CS approach provides the best performance across all input amplitude, frequency and shapes. A capacitive water level sensor was implemented in a PCB and embedded in a conventional square wave relaxation oscillator to verify the proposed technique. Measurement results show that incremental SNRs can be achieved only by increasing the 1-bit data stream length without any change in the hardware thereby demonstrating the adaptability of the technique based on an application requirement.

Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks

Recent research shows that 4-bit data precision is sufficient for Deep Neural Network (DNN) inference without accuracy degradation. Due to the low bit-width, a large amount of data is repeated. In this article, we propose a hardware architecture, named Rare Computing Architecture (RCA), that skips redundant computations due to repetitive data in the networks. By exploiting redundancy, RCA is not significantly affected by data-sparsity and maintains great improvements in performance and energy efficiency, while the improvements of existing DNN accelerators are vulnerable to variations in sparsity. In the RCA, repeated data in a window for censoring repetition are detected by a Redundancy Censoring Unit (RCU) and processed at a time, achieving high effective throughput. Additionally, we present a dataflow that exploits abundant data-reusability in DNNs, which enables the high-throughput computations to be ceaselessly performed without an increase of bandwidth for data-read. The proposed architecture is evaluated in two ways of exploiting weight- and activation-repetition. In the evaluation, RCA is compared to a value-agnostic computation and UCNN that is the state-of-the-art accelerator exploiting weight-repetition. Additionally, RCA is compared to Bit-pragmatic that exploits bit-level sparsity. Both evaluations demonstrate that the RCA shows steadily high improvements in performance and energy-efficiency.

Target Detection and Classification Improvements using Contrast Enhanced 16-bit Infrared Videos

In our earlier target detection and classification papers, we used 8-bit infrared videos in the Defense Systems Information Analysis Center(DSIAC) video dataset. In this paper, we focus on how we can improve the target detection and classification results using 16-bit videos. One problem with the 16-bit videos is that some image frames have very low contrast. Two methods were explored to improve upon previous detection and classification results. The first method used to improve contrast was effectively the same as the baseline 8-bit video data but using the 16-bit raw data rather than the 8-bit data taken from the avi files. The second method used was a second order histogram matching algorithm that preserves the 16-bit nature of the videos while providing normalization and contrast enhancement. Results showed the second order histogram matching algorithm improved the target detection using You Only Look Once (YOLO) and classificationusing Residual Network (ResNet) performance. The average precision (AP) metric in YOLO was improved by 8%. This is quite significant. The overall accuracy (OA) of ResNet has been improved by 12%. This is also very significant.

Highly accurate and efficient cluster validation index engine using global separation and local dispersion architecture for adaptive image clustering systems

This paper presents a novel cluster validity index (CVI) engine based on global separation and local dispersion (GSLD) used to improve the accuracy and calculation efficiency of adaptive image clustering systems. The proposed GSLD engine can efficiently improve upon traditional GSLD calculation speed by making full leverage of temporary computation results obtained during the image clustering process itself. The CVI large-scale integrated (LSI) engine, designed with 55 nm CMOS technology, successfully achieves a 200 MHz GSLD calculation rate within 268 clocks using 8-bit data precision. In addition, by comparing various conventional CVI methods, the proposed CVI engine’s superiority is demonstrated by the deployment of real-life images and complex artificial datasets with different sizes, densities, and even overlaps. The experimental result reveals that the GSLD architecture’s computational complexity is reduced by 88.9% compared with the conventional variance ratio criterion (VRC) CVI and general GSLD calculation.

Target Detection and Classification Improvements using Contrast Enhanced 16-bit Infrared Videos

In our earlier target detection and classification papers, we used 8-bit infrared videos in the Defense Systems Information Analysis Center(DSIAC) video dataset. In this paper, we focus on how we can improve the target detection and classification results using 16-bit videos. One problem with the 16-bit videos is that some image frames have very low contrast. Two methods were explored to improve upon previous detection and classification results. The first method used to improve contrast was effectively the same as the baseline 8-bit video data but using the 16-bit raw data rather than the 8-bit data taken from the avi files. The second method used was a second order histogram matching algorithm that preserves the 16-bit nature of the videos while providing normalization and contrast enhancement. Results showed the second order histogram matching algorithm improved the target detection using You Only Look Once (YOLO) and classification using Residual Network (ResNet) performance. The average precision (AP) metric in YOLO was improved by 8%. This is quite significant. The overall accuracy (OA) of ResNet has been improved by 12%. This is also very significant.

IMPLEMENTATION OF A REDUCED COMPLEXITY HIGH PERFORMANCE DATA ACQUISITION CHIP USING 0.18 MICRON TECHNOLOGY

Data acquisition (DAQ) in the general sense is the process of collecting information from the real world. For engineers and scientists, this data is mostly numerical and is usually collected, stored and analysed using computers. However, most of the input signals cannot be read directly by digital computers. Because they are generally analog signals distinguished by continuous values, while computers can only recognise digital signals containing only the on/off levels. DAQ systems are therefore inevitably necessary, as they include the translation requirements from analog signals to digital data. For this reason, they have become significant in wide range of applications in modern science and technology [1]. The paper precents the disign of a 12-bit high-speed low-power Data Acquisition (DAQ) Chip. In this paper, the disigns of the building block components are aimed at high-accuracy along with high-speed and low power dissipation. A modifided flash Analog-to-Digital converter (ADC) was used instead of the traditional flash proposed DAQ chip operates at 1 GHz master clock frequency and achieves a sampling speed of 125 MS/s. It dissipates only 64.9 mW of power as compared to 97.2 mW when traditional flash ADC was used.

Efficient Implementation of AES and CTR_DRBG on 8-Bit AVR-Based Sensor Nodes

Since Rijndael algorithm was selected as the Advanced Encryption Standard (AES) by NIST, optimization research for the AES has been actively conducted on various IoT-based processors. In an 8-bit AVR environment, LIGHT version of Fast AES CTR-mode Encryption (FACE-LIGHT) was proposed at ICISC'2019 conference. However, in a Wireless Sensor Network environment, where sessions are frequently changed, FACE-LIGHT seems not efficient in terms of available memory and generating a pre-computation table. In this article, we present a new column-wise fashion implementation. Unlike previous best AES implementations, our proposed implementation in an 8-bit AVR microcontroller combines SubBytes, ShiftRows, and MixColums operations and optimizes the operation speed through efficient register scheduling. Our constant-time implementation uses a significantly less table than FACE-LIGHT in an 8-bit AVR microcontroller, achieving 2,251, 2,706, and 3,160 clock cycles when encrypting 128-bit data for each of three security levels. In particular, our 256-bit security level AES implementation is the fastest AES implementation as far as we know in 8-bit AVR microcontroller. Finally, we apply our implementation in CounTeR-mode_Deterministic Random Bit Generator (CTR_DRBG), one of the upper algorithms of a symmetric-key algorithm, to prove the generality of our optimization technology in various operating modes of AES.

A GPU-Accelerated Modified Unsharp-Masking Method for High-Frequency Background- Noise Suppression

A digitized analog signal often encounters a high-frequency noisy background which degrades the signal-to-noise ratio (SNR) particularly in case of low signal strength. Despite quite a lot of hardware- and software-based approaches have been reported to date to deal with the noise issue, it is still a challenging task to real-time retrieve the noise-contaminated low-frequency information efficiently without degrading the original bandwidth. In this paper, we report a modified unsharp-masking (UM)-based Graphics Processing Unit (GPU)-accelerated algorithm to efficiently suppress a high-frequency noisy background in a digitized two-dimensional image. The proposed idea works effectively even if noise-density is high and signal of interest is comparable or weaker than the maximum noise level. While suppressing the noisy background, the original resolution remains least compromised. We first explore the effectiveness of the algorithm by means of simulated images and subsequently extend our demonstration towards a real-world life-science imaging application. Securing a potential for real-time applicability, we implement the algorithm via Compute Unified Device Architecture (CUDA)-acceleration and preserve a <; 300 μs processing time for a 1000×1000-sized 8-bit data set.

Design, Implementation, and Analysis of High-Speed Single-Stage N-Sorters and N-Filters

There is strong interest in developing high-performance hardware sorting systems which can sort a set of elements as quickly as possible. The fastest of the current FPGA systems are sorting networks, in which sets of 2-sorters operate in parallel in each series stage of a multi-stage sorting process. A 2-sorter is a single-stage hardware block which sorts two values, so any list with more than 2 values must be sorted with a series network of 2-sorters. A primary contribution of this work is to provide a general methodology for the design of stable single-stage hardware sorters which sort more than 2 values simultaneously. This general methodology for $N$ -sorter design, with $N{>}2$ , is then adapted for use in modern FPGAs, where it is shown that single-stage 3-sorters up to 9-sorters have speedup ratios from 2.0 to 3.5 versus the comparable state-of-the-art 2-sorter networks. A design system modification is shown to produce even faster single-stage $N$ -max and $N$ -min filters. When used for max pooling 32-bit data in the fastest analyzed FPGA, a single 9-max filter will process 500 million 9-pixel groups per second (4K:3840x2160 at 500 frames/second). The single-stage 9-median filter using this design methodology, useful in image processing, is shown to have speedup ratios of 3.0 to 4.1 versus state-of-the-art FPGA network implementations, even though its resource usage is comparable to, often better than, the network implementations. Ten 8-bit 9-median filters operating in parallel in the fastest FPGA will process over 5.4 billion pixels/sec (4K at over 600 frames/second).

Design and analysis of a Reconfigurable Intelligent Meta-surface for vehicular networks

In this work, a new paradigm for vehicular communications based on Reconfigurable Intelligent Meta-surfaces (RIMs) is presented. By using the proposed RIM, we are able to manipulate electromagnetic waves in the half-space, since the element is reflective. The unit cell consists of a U-shaped designed microstrip structure equipped with a pin diode and via a hole. In this study, two different reflection modes are achieved for 1-bit data transferring in each state. By incorporating these two different configurations together, the reflected phases in the proposed RIM surface can be controlled respectively in 0 and 180. The proposed unit cell can provide a usable double negative functional characteristic around 5.3 GHz. The main goal of this paper is the use of a multifunctional behavior RIM for vehicular communications to code the transmitted wave. A novel phase distribution diagram is generated to propagate in each angle. Moreover, two major electromagnetic modulation functions, beam forming and space coding have been demonstrated. Finally, we show how the RIM can be employed for vehicular communications, acting as a coated access point along the street. We derive the instantaneous data rate at the receiver node, the outage probability and the channel capacity, as affected by different beam widths, distances and vehicle speed.

An octagonal-shaped conductive HC12 & LIBERATOR-40 thread embroidered chipless RFID for general IoT applications

This paper presents the design, fabrication and testing of two embroidered chipless octagonal-shaped RFID tags on cotton fabric for wearable applications. The first tag is designed by using silver-coated polyamide conductive fibre (HC12) and the second tag is embroidered by using highly conductive Vectran (LIBERATOR 40) which is highly conductive multifilament yarn spun from Liquid Crystal Polymers (LCP), on cotton fabrics. In contrast to the traditional RFID tag, the chipless RFID tagging, the ID code is not saved in the memory, instead, it uses the physical features of the tag to send data. The proposed tag's design uses a Frequency Selective Surface (FSS) technique for the frequency range of 8–18 GHz. These tags are designed using CST studio and precisely fabricated by using commercial ZSK Technical Embroidery System JCZA (0109–550). The tag design is composed of six concentric octagonal loop resonators with one unitary element. The electromagnetic scattering waves behaviour and Singularity Expansion Method (SEM) based circuit modelling for the octagonal-shaped tag is performed, and the coupling coefficients are evaluated. The desired data bits are obtained by a series of comparative experiments for Radar Cross Section (RCS) in an anechoic chamber. The experimental results obtained show that the 4-bit data is accurately retrieved with the variation of distance by up to 1.8 m at 0 dB m. Moreover, the average transition from minimum ‘0’ to maximum 1’ is -27 dB for both designs. Furthermore, the experimental results for on-body RCS measurements and the bending effects on both tags down to 7 mm is observed. This octagonal embroidered Chipless RFID tag is a fully textile design which is compact and can be deployed commercially in various IoT applications.

Multi-dimensional cubic symmetric block cipher algorithm for encrypting big data

The advanced technology in the internet and social media, communication companies, health care records and cloud computing applications made the data around us increase dramatically every minute and continuously. These renewals big data involve sensitive information such as password, PIN number, credential numbers, secret identifications and etc. which require maintaining with some high secret procedures. The present paper involves proposing a secret multi-dimensional symmetric cipher with six dimensions as a cubic algorithm. The proposed algorithm works with the substitution permutation network (SPN) structure and supports a high processing data rate in six directions. The introduced algorithm includes six symmetry rounds transformations for encryption the plaintext, where each dimension represents an independent algorithm for big data manipulation. The proposed cipher deals with parallel encryption structures of the 128-bit data block for each dimension in order to handle large volumes of data. The submitted cipher compensates for six algorithms working simultaneously each with 128-bit according to various irreducible polynomials of order eight. The round transformation includes four main encryption stages where each stage with a cubic form of six dimensions.

High signal-to-noise ratio reconstruction of low bit-depth optical coherence tomography using deep learning.

.Significance: Reducing the bit depth is an effective approach to lower the cost of an optical coherence tomography (OCT) imaging device and increase the transmission efficiency in data acquisition and telemedicine. However, a low bit depth will lead to the degradation of the detection sensitivity, thus reducing the signal-to-noise ratio (SNR) of OCT images.Aim: We propose using deep learning to reconstruct high SNR OCT images from low bit-depth acquisition.Approach: The feasibility of our approach is evaluated by applying this approach to the quantized 3- to 8-bit data from native 12-bit interference fringes. We employ a pixel-to-pixel generative adversarial network (pix2pixGAN) architecture in the low-to-high bit-depth OCT image transition.Results: Extensively, qualitative and quantitative results show our method could significantly improve the SNR of the low bit-depth OCT images. The adopted pix2pixGAN is superior to other possible deep learning and compressed sensing solutions.Conclusions: Our work demonstrates that the proper integration of OCT and deep learning could benefit the development of healthcare in low-resource settings.

Efficient Design of Pruned Convolutional Neural Networks on FPGA

Convolutional Neural Networks (CNNs) have improved several computer vision applications, like object detection and classification, when compared to other machine learning algorithms. Running these models in edge computing devices close to data sources is attracting the attention of the community since it avoids high-latency data communication of private data for cloud processing and permits real-time decisions turning these systems into smart embedded devices. Running these models is computationally very demanding and requires a large amount of memory, which are scarce in edge devices compared to a cloud center. In this paper, we proposed an architecture for the inference of pruned convolutional neural networks in any density FPGAs. A configurable block pruning method is proposed together with an architecture that supports the efficient execution of pruned networks. Also, pruning and batching are studied together to determine how they influence each other. With the proposed architecture, we run the inference of a CNN with an average performance of 322 GOPs for 8-bit data in a XC7Z020 FPGA. The proposed architecture running AlexNet processes 240 images/s in a ZYNQ7020 and 775 images/s in a ZYNQ7045 with only 1.2% accuracy degradation.

Binary sequence matching system based on cross-phase modulation and four-wave mixing in highly nonlinear fibers

Photonic firewalls that can directly conduct the data discrimination and intrusion detection at the optical layer are an important security technique for optical networks. In the photonic firewall, binary sequence matching module is the core part and is implemented by multiple all-optical logic gates such as all-optical AND gate, all-optical XOR gate, etc. However, the semiconductor optical amplifier (SOA)-based all-optical logic gates have the disadvantages of low operation rate which leads to low matching rate. We design a binary sequence matching module that is implemented by the cross-phase modulation effect (XPM) and the four-wave mixing effect (FWM) of the highly nonlinear fiber (HNLF). The nonlinear effect of HNLF has a very short response time, thus it can realize the logic operation at a very high optical signal rate. The developed binary sequence matching module is verified through VPI Transmission Maker 8.5. The simulation results show that it can achieve the matching of 8-bit data in 64-bit binary data at 160-Gbps signal rate.

Continuous-Flow Matrix Transposition Using Memories

In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of $8192 \times 8192$ 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.

Design of an 8-bit Bit-Parallel RSFQ Microprocessor

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

2D Parity Product Code for TSV online fault correction and detection

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults. In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code. In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction.

Interconversion of complementary resistive switching from graphene oxide based bipolar multilevel resistive switching device

In this work, organic material-based resistive switching mechanisms were studied by using graphene oxide as the switching layer. With the insertion of a charge trapping graphene layer, the device showed good stability and good electrical bipolar switching properties, with an ON/OFF ratio about 102–103. The device gradually shifted toward complementary switching behavior while maintaining an ON/OFF ratio of ∼102 from bipolar switching behavior after a specific number of consecutive DC switching cycles with increases in the SET-RESET voltage. The conduction mechanisms for bipolar (P–F conduction) and the complementary switching were verified based on the electrical characteristics and curve fittings. Rapid increases in the injected electrons due to increased voltage in complementary switching facilitated the formation of an intermediate charge reservoir region that, in turn, enhanced performance. The device showed a retention period as high as 104 s at 85 °C and good DC endurance. The device is also capable of multi-resistance states to obtain multi-bit (4-bit) data storage, leading to high density memory realization.

Improved KASUMI block cipher for GSM-based mobile networks

ABSTRACT KASUMI is an eight-round Feistel network that produces 64-bit output from 64-bit input by using 128-bit key. Three functions FL, FO and FI are involved in each round and each function has its respective keys KL, KO and KI . In this work, modifications in the existing KASUMI are proposed to reduce the encryption time. In proposed KASUMI, the single FL function is divided into two functions such as FLleft and FLright. The FLleft function is constructed with two Rijndael’s 32-bit S -boxes. The FLright function is constructed with four stages where third and fourth stages are performing XOR and shift operations before final concatenation of two 16-bit data of FL function. The simulation results are provided in terms of encryption time taken versus number of iteration and encryption speed versus number of iteration to show that the proposed KASUMI block cipher design outperforms the conventional KASUMI block cipher.