10-bit Analog-to-digital Converter Research Articles

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.

A subranging nonuniform sampling memristive neural network-based analog-to-digital converter

This work presents a novel 4-bit subranging nonuniform sampling (NUS) memristive neural network-based analog-to-digital converter (ADC) with improved performance trade-off among speed, power, area, and accuracy. The proposed design preserves the memristive neural network calibration and utilizes a trainable memristor weight to adapt to device mismatch and increase accuracy. Rather than conventional binary searching, we adopt quaternary searching in the ADC to realize subranging architecture’s coarse and fine bits determination. A level-crossing nonuniform sampling (NUS) is introduced to the proposed ADC to enhance the ENOB under the same resolutions, power, and area consumption. Area and power consumption are reduced through circuit sharing between different stages of bit determination. The proposed 4-bit ADC achieves a highest ENOB of 5.96 and 5.6 at cut-off frequency (128 MHz) with power consumption of 0.515 mW and a figure of merit (FoM) of 82.95 fJ/conv.

A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers

To address the problem of low trigger accuracy during trigger resampling and variable sampling rate trigger resampling using a fixed sampling rate analog-to-digital converter (ADC), this paper proposes an interpolation method combining sinc interpolation and linear interpolation to improve accuracy, based on a digital trigger. After behavior simulation verification and actual field programmable gate array (FPGA) test verification, the data collected by two 3GSps 12-bit ADCs were subjected to 8-times sinc interpolation followed by 16-times linear interpolation processing, after which the original trigger resampling accuracy was increased by 128 times and the sampling rate could be realized to vary between 100 MHz and 1 GHz. A signal–noise ratio (SNR) of 46.80 dBFS, a spurious free dynamic range (SFDR) of 45.91 dB, and an effective number of bits (ENOB) of 7.48 bits were obtained by direct trigger resampling without algorithm processing in the behavior simulation. Meanwhile, an SNR of 58.98 dBFS, an SFDR of 60.96 dB, and an ENOB of 9.42 bits were obtained by trigger resampling after algorithm processing. Due to the influence of analog link signal loss and signal interference on the development board, an SNR, SFDR and ENOB of 51.97 dBFS, 61.26 dB, and 8.32 bits, respectively, were obtained from the trigger resampling in the FPGA test. The experimental results show that the algorithm has not only improved the triggering accuracy but has also improved the SNR, SFDR, and ENOB parameters.

Virtual-carrier-assisted 12 Gb/s 64QAM millimeter-wave signal transmission at 30 GHz using a 4-bit digital-to-analog converter.

We propose and experimentally demonstrate a radio-frequency digital resolution enhancer (RF-DRE) to mitigate the quantization noise of the RF signal induced by the low-resolution digital-to-analog converter (DAC) in the virtual-carrier-assisted millimeter-wave (mm-wave) signal transmission system. By introducing a bandpass filter (BPF) as the reference for the RF-DRE algorithm, we can design the quantization noise and shape its spectrum inversely to the bandpass filter. By these means, the quantization noise in the target RF frequency range can be effectively mitigated. In the simulation, the bit error rate (BER) of a 4-bit DAC-quantized 16 Gb/s 256QAM signal at 30 GHz is improved from 3.36e-2 to 7.43e-3 by using the RF-DRE. In our experiment, 30 GHz virtual-carrier-assisted mm-wave transmission of 12 Gb/s 64QAM signals over 25 km of standard signal mode fiber (SSMF) is realized. By using the RF-DRE, the BER of a 4-bit DAC-quantized signal can be improved from 6.88e-3 to 1.49e-3, and a 5-bit DAC exhibits a similar performance to an 8-bit DAC without the RF-DRE. Therefore, low-resolution and low-cost DACs can be used for mm-wave signal generation with the help of the proposed RF-DRE.

A column-parallel 1-bit ADC with threshold offset reduction technique for single-bit quanta image sensor

This paper presents a column-parallel 1-bit analog-to-digital converter (ADC) with threshold offset reduction technique, which aims to reduce the bit error rate (BER) of single-bit quanta image sensor (QIS). The fixed offset of the differential charge transfer amplifier (DCTA) and the fixed compensation offset of the calibrated dynamic latch (CD-latch) comparator are eliminated by two coupling capacitors. Additionally, an improved 3-stage DCTA with low gain error is designed to further suppress the fixed residual offset of the CD-latch. The proposed circuit is implemented by a 110 nm CMOS process. Post-simulation results show that the proposed 1-bit ADC achieves a threshold offset of 32.6 μV at 4 MSa/s sampling rate and 500 μV quantization threshold. Compared with the conventional structure, the random noise of the proposed 1-bit ADC remains almost unaltered. Meanwhile, its threshold offset is lowered by 153.6 μV, making the model BER and circuit BER of the column-level circuit reduce from 2.42% to 0.21% and 2.29%–0.26%, respectively.

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

A VCO-Based 2nd-Order Δ2–ΔΣ Modulator for Small-Size High Energy-Efficient Current Sensing Front-End

In this letter, a 2nd-order 2 -Σ modulator consisting of a voltage-controlled-oscillator-based quantizer (VCOQ) and a current digital-to-analog converter (DAC) with a pulse width modulator (PWM) is presented for the precise acquisition of a wide range photocurrent in an area-and energy-efficient form factor. The proposed 2-modulation realized by the 2nd-order infinite impulse response (IIR) filter on the feedback significantly attenuates the magnitude of input signals, enhancing the DR and linearity. Moreover, an additional differentiator followed by the VCOQ features the negative feedback loop in the 2nd-order Σ modulator, improving noise shaping with no additional current DAC noise. In addition, a 1-bit PWM current DAC substituting the multi-bit current DAC is devised to mitigate the noise from the current DAC, realizing the high resolution of 1 pA with 500 Hz bandwidth. The prototype chip fabricated in a 110-nm CMOS occupies 0.0308 mm2 and achieves Walden FoM of 4.15 pJ/conv.

A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported.

A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme

A low-power 12-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a reversible VCM-based capacitor (RVC) switching scheme is presented in this paper. The switching power consumption of the proposed scheme is 95% and 62.3% lower than that of conventional and VCM-based capacitor switching schemes, respectively. The use of a segmented DAC structure reduces the size of the largest capacitor from 211 unit capacitors in the conventional capacitor array to 24 unit capacitors. This 75% reduction in the capacitor area decreases the settling time of the DAC capacitor network as well as requirements on the bandwidth and driving capability of the reference source VREF. An ADC prototype with an active area of 0.218 mm2is fabricated in 180-nm 1P6M CMOS process. With supply of 1.8 V and sampling rate of 10 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 58.9 dB and consumes power of 0.36 mW, yielding a figure of merit (FOM) of 59.8fJ/conversion-step.

A low‐power and area‐efficient ultrasound receiver using beamforming successive approximation register analog‐to‐digital converter with capacitive digital‐to‐analog converter combined delay cell structure for 3‐D imaging systems

The authors present a low-power area-efficient subarray beamforming receiver (RX) structure for a miniaturized 3-D ultrasound imaging system. Given that the delay-and-sum (DAS) and digitization functions consume most of the area and power in the receiver, the beamforming successive approximation register (SAR) analog-to-digital converter (ADC) shares its capacitive digital-to-analog converter (CDAC) with the delay cells. As a result, the delay cells implemented with capacitors are embedded in the CDAC with significant area reduction, further eliminating the need for power-hungry ADC buffers. Furthermore, the dual reference 10-bit SAR ADC reduces the area of CDAC by 32 times, achieving a switching energy reduction of 98.3%, compared to the conventional SAR ADC. As a result, the proposed beamforming SAR ADC, simulated using a 0.18 μm CMOS process, consumes 230 μW per channel, significantly reducing the per channel capacitance.

Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals

Low-activity signals, such as voice, electrocardiogram (ECG), and ultrasonic signals, in the Internet-of-Things applications have both posed unique challenges and offered special opportunities for modern analog-to-digital conversion. This article presents a new successive approximation register (SAR) analog-to-digital converter (ADC) search methodology, which is aimed at low-activity signals for reducing comparator activity and switching energy of digital-to-analog converter (DAC). By using statistical histogram information of the low-activity signals, two search solutions are proposed. The first solution is designed for some part of signal that has small difference between two adjacent samples, while the second solution is designed for that with large difference. To engage one suitable solution, the digital interval between two adjacent samples needs to be detected. In addition, a new DAC tactic is proposed to reduce the activity of DAC switches. Our simulated 10-bit SAR ADC for voice signals shows that by using our proposed method, the comparator activity is reduced by 62.09%, and the DAC switching energy is decreased by 85.90% compared to the monotonic method. In addition, the activity of DAC switches is further trimmed by 39.66% compared to the monotonic method.

A dither‐less bit weight digital background calibration for bridge capacitor digital‐to‐analog converter successive approximation register analog‐to‐digital converters

The authors present a dither-less background digital bit weights calibration method for split-capacitor digital-to-analog converter (CDAC) successive approximation register (SAR) analog-to-digital converters (ADCs) to improve non-linearities caused by capacitor mismatch and bridge-capacitor inaccuracy errors in a split-CDAC. By using a digital pseudo-random number (PN) generator and paired comparators with opposite offsets, a dither-less background calibration quickly reaches the target signal-to-noise-and-distortion ratio (SNDR) within 5 × 104 samples for various process uncertainties. The simulated performance using a behavioural 6-bit + 6-bit ADC with 1-bit redundancy for various random offset and capacitor mismatches shows that the SNDR increases from 45.7 to 65.7 dB after the calibration.

A novel noncoupling capacitor split capacitor array structure for high resolution SAR ADC

In order to achieve high resolution in Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a novel noncoupling capacitor split capacitor array structure is proposed, which solves the coupling capacitor mismatch problem in the traditional split capacitor array structure. This paper analyzes the structure and its capacitor array mismatch. Based on the structure and analysis, a 12-bit SAR ADC is designed and implemented in GSMC 0.11 [Formula: see text]m CMOS process. The measured results show that the Signal to Noise Ratio (SNR) is 72.61 dB and Effective Number Of Bits (ENOB) is 11.77 bit, which prove the advantages of this structure in the design of high resolution SAR ADC.

Development of an on-chip configurable DAC module for monolithic active pixel sensor

This paper describes an on-chip configurable Digital to Analog Converter (DAC) module for monolithic active pixel sensor. The DAC module consists of four 10-bit voltage DACs, seven 8-bit current DACs, a bandgap circuit, and a configure interface. The voltage DAC is implemented with an R-2R resistor ladder network, and each LSB corresponds to 3 mV. The current DAC is in the current-steering type with a thermometer code. Each LSB of the current DAC corresponds to 10 nA. The bandgap circuit provides a stable, temperature-independent reference voltage of 1.25 V to the DACs. All the DACs can be accessed and configured with the configure interface. The DAC module covers 3074 µm × 400 µm, and the total power consumption is 46.2 mW. This paper will discuss the design and performance of this DAC module.

A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator

This paper presents a low-power asynchronous 10-bit 2-then-1b/cycle successive approximation register (SAR) analog-to-digital converter (ADC). With partial adoption of 2b/cycle mode only for higher-order bit conversions, additional area and power consumption could be minimized while maintaining fast conversion rate. Moreover, unlike the previous 2b/cycle conversion architecture, where two capacitive digital-to-analog converters (C-DACs) and multiple analog comparators are unavoidable, the proposed 2-then-1b/cycle conversion is implemented with only one C-DAC and one analog comparator by utilizing a digital-based time-domain reference. The speed of 1b/cycle conversion for lower-order bits is improved with a dual-mode comparator. With the aforementioned techniques, the prototype 10-bit SAR ADC is fabricated in 65 nm CMOS process. The ADC core occupies an active area of 0.0142 mm2 and consumes power of 3.8 μW at 0.5 V supply voltage and 3 MS/s conversion rate. The SNDR measured at a Nyquist-rate input frequency is 56.41 dB, resulting in a figure of merit (FoM) is 2.33 fJ/c.-s.

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step.

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

This paper presents a digital background technique that intentionally exploits multiple dithers to calibrate conversion errors caused by interstage gain error and nonlinearity in high speed pipelined analog-to-digital converters (ADCs). Two independent, zero-mean pseudo-random signals are injected into the multiplying digital-to-analog converter (MDAC) alternately to estimate these errors. Least mean square (LMS) algorithms are adopted to quickly locate and track the calibration parameters. Simulation results are presented for a 800 MSps 12-bit pipelined ADC in a 40nm CMOS technology, similar to that described by Murmann and Boser [1], Keane et al. [2] and Nan Sun [3] using low-gain amplifiers. With calibration, the signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.74dB and 43.61dB to 70.54dB and 89.8dB, respectively. The proposed calibration technique has the advantages of simple implementation, arbitrary amplitude pseudo-random signals, and no restriction on the input signal of the ADC.

Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes. The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor (CMOS) library using Cadence Virtuoso design tool. Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3% compared with conventional SAR ADC, compared with the SAR ADC with split capacitor, and compared with the resistor and capacitor (R&C) Hybrid SAR ADC. The ADC achieves an effective number of bits (ENOB) of bits and consumes at sampling rate of , offering an energy consumption of per conversion step. The proposed SAR ADC offers 95.5% reduction in chip core area compared to conventional architecture, while occupying an active area of .

A MEMS-CMOS Microsystem for Contact-Less Temperature Measurements

This paper presents a microsystem suitable for contact-less human body temperature measurements, as well as for presence, motion and proximity detection. It consists of a 130-nm CMOS-SOI MEMS (Micro-Electro Mechanical System) thermal sensor, referred to as &#x201C;TMOS&#x201D;, and its 130-nm CMOS interface circuit. The TMOS, based on a micromachined transistor, being an active device, features advantages in terms of internal gain: with optimal biasing, indeed, the TMOS achieves 274-<inline-formula> <tex-math notation="LaTeX">$\mu \text{V}/^\circ \text{C}$ </tex-math></inline-formula> input-referred sensitivity at 3-cm distance and 50.33&#x00B0; field-of-view (FOV), outperforming thermopile detectors. The sensor and the interface circuit, featuring a chopper-stabilized-based analog readout with a 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter), were mounted in the same package and extensively measured: the microsystem achieves repeatability and &#x00B1;0.17&#x00B0;C precision, thus satisfying the requirements for contact-less human body temperature measurements; furthermore, its performance as presence, motion and proximity detector was also verified.