32-bit ALU Research Articles

Phonon-limited mobility and quantum transport in fluorinated diamane MOSFETs from the first-principles calculations

Two-dimensional diamane with outstanding properties is promising for advanced nanodevice applications, whereas a comprehensive understanding of phonon-limited mobility as well as the prediction of device performance limit is still lacking. Here we report on phonon-limited mobility simulation in fluorinated diamane monolayer using first-principles calculations, with consideration of both elastic and inelastic phonon scattering processes based on Boltzmann transport equation. We construct sub-7 nm fluorinated diamane metal-oxide-semiconductor field-effect transistors (MOSFET) to investigate their quantum transport properties by first-principles calculations based on density functional theory coupling with the non-equilibrium Green's function formalism. Our findings show that fluorinated diamane mobility is concentration-dependent, with the electron and hole mobility reaching as high as 4390 and 10100 cm2V−1s−1, respectively, at the 1014 cm−2 carrier concentration. Our simulations reveal that the key figures of merits (FOMs) of fluorinated diamane MOSFETs are benchmarked against the International Technology Roadmap for Semiconductors (ITRS) standards for high-performance (HP) and low-power (LP) applications, showing superior potential compared to the most reported 2D materials. The simulated results demonstrate that the on-current, delay time, and power-delay product meet the ITRS requirements for HP and LP applications, including devices constructed with nano-scale channel length (≥3 and 5 nm) respectively. Finally, we show that the performance of a 32-bit ALU based on fluorinated diamane MOSFETs is comparable with emerging beyond-CMOS devices. Thus, our results shed light on the electronic properties of fluorinated diamane, making it superior to serve as a channel material in the post-silicon era.

An extensible architecture of 32-bit ALU for high-speed computing in QCA technology

An extensible architecture of 32-bit ALU for high-speed computing in QCA technology

32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor

32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor

Efficient Multiple 4-Bit ALU Designs for Fast Computation and Reduced Area

Efficient Multiple 4-Bit ALU Designs for Fast Computation and Reduced Area

AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme.

Design and Implementation of an Optimum VLSI Based 16-BIT ALU

Design and Implementation of an Optimum VLSI Based 16-BIT ALU

FinFET based Design and Performance Analysis of Nano-processor for Low Area, Low Power and Minimum Delay using 32nm

The recent technologies in VLSI chips has grown in terms of scaling of transistor and device parameters but still there is a challenging task for controlling of current between source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip manufacturing, through which current can be effectively controlled. This section addresses the issues present in CMOS technology and majorly concentrated on proposed 4-bit Nano processor using FinFET 32nm technology by using Cadence Virtuoso software tool. In the proposed Nanoprocessor design, the first portion of the design is done using 4bit ALU which includes all basic and universal gates, high speed adder, multiplier and multiplexer. The Carry Save Adder (CSA) and multiplier are the major sub component which can optimize the power consumption and area reduction. The second portion of the proposed Nano processor design is 4-bit 6T SRAM and encoder and decoder and also using Artificial Neural Network (ANN). All these sub components are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS and at the last chip level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET using technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% with optimization in power dissipation of 47% along with optimization in leakage current, with 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses are compressed subsequently respectively. The basic gates, universal gates, CSA, subtraction and MUX are integrated for 4-bit ALU design and its delay, power consumption and area are found to be 0.104nsec, 314.4uW and 56.8μsqm respectively.

Design of High Performance ALU Using Vedic Mathematics

This article proposes a Vedic multiplier-based design of multiply and accumulate unit by employing UrdhvaTiryagbhyam Sutra. Further, it implements an efficacious ALU with 32-bit architecture. Simulation analysis disclosed the comparison of proposed 32-bit ALU with existing architectures. In addition, complexity in hardware, area and delay reduction demonstrated that proposed 32-bit ALU is more efficient over conventional architectures.

English

Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.

Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

WITHDRAWN: Performance analysis and design of finfet 32 nm based low power, low delay 4-bit alu, carry save adder and multiplier for high speed processors

Abstract The limitations of CMOS technology are short channel effects, battery powered problem, power dissipation, delay. All digital circuits like logical and arithmetic operations are performed and designed using CMOS. The power dissipation/consumption in such circuits are more so the fast growing technology requires the lower power dissipation/consumption, low leakage currents and lessor short channel effects. Therefore, to address these issues, the proposed research work has introduced FinFET 32 nm technology for the designing of logical operation, arithmetic, multiplexer, 4-bit ALU, Carry Save Adder (CSA) and multiplier using Cadence Virtuosos software tool. Another challenge in CMOS technology is, size of the transistor which is used to measure area, therefore the proposed research work, optimize the delay, power, W/L ratio and also no of transistors for designing of both gates and arithmetic operations. The work has been carried out from schematic level to layout design to Graphic Data System (GDS II) generation. To validate the FinFET based ALU and multiplier, its detailed analysis of the constraints related to FinFET transistor level and benefits, in which each transistor is modified for the delay at different timings arcs and power consumption, are done. The individual gate and arithmetic operations are tested and calculated in which the delay and power consumption are compared with existing work and it is found that the reduction in the power level for AND, XOR, OR, NAND, NOT gates, full adder, CSA, 2bit multiplier and ALU are 36.09 nW, 61.13nW, 64.97nW, 37.45nW, 33.31nW, 38.22nW, 2.39 μW, 39.89nW and 314.4 μW respectively.

Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

The conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to the netlists of RSFQ circuits, considering the reduction of the number of clocked gates, including D flip-flops (DFFs) for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer that can be utilized for realizing logic-or. The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. The detection methods of replaceable gates with those two kinds of gates are proposed. An automatic test pattern generation tool is utilized for detecting replaceable or gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering the cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and the assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU, and a 64-bit ALU. The evaluation results show that the number of clocked gates and the latency in the cycles of circuits is reduced by about 10%. The delay time of the converted circuits has been estimated and the reduction of delay overhead is discussed.

Design and Implementation of 4-Bit ALU for Low-Power using Adiabatic Logic based on FINFET

Design and Implementation of 4-Bit ALU for Low-Power using Adiabatic Logic based on FINFET

Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.

Leakage Power Minimization using IVC based GSA

The power management has become the major constraint while designing VLSI circuits as parameters like Area, Speed, etc. are critical to be optimized. In this work, a low power 16-bit ALU is designed to perform all arithmetic and logic operations. The present day super computers, mobile gadgets, calculators etc. are using low power ALU systems to perform their tasks. Especially, leakage power occupies major portion of power consumption in the CMOS circuits, as the process technology progresses. The objective of the research work is to reduce leakage power in maximum extent to run the ALU with low power. The proposed model has used IVC based leakage power reduction technique in standby mode by using Gravitational Search Algorithm (GSA). Input Vector Control (IVC) technique is found to be a better alternative in achieving low leakage as it is based on the effect of transistor stacking and it is highly preferred because of its independency over other technological parameters without performance overhead. The GSA locates MLV (Minimum Leakage Vector) in vector combinations of input test circuits of ALU. And then IVC forces the other vector combinations into MLV mode of a test circuit to reduce leakage power. The comparison study has been carried out with Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) algorithm with various test circuits. Power analysis is conducted with GSA to ascertain better leakage reduction and also it locates MLV in less number of iterations. GSA takes only 13 iterations to reach its global space, whereas, PSO takes 62 iterations and GA takes 96 iterations to reach their global space. The simulations are carried out using the Xilinx platform with Verilog coding using PSPICE and MATLAB tools.

Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems

Adiabatic Quantum-Flux-Parametron (AQFP) logic is an adiabatic superconductor logic family that has been proposed as a future technology towards building extremely energy-efficient computing systems. In AQFP logic, dynamic energy dissipation can be drastically reduced due to the adiabatic switching operations using AC excitation currents, which serve as both clock signals and power supplies. As a result, AQFP could overcome the power/energy dissipation limitation in conventional superconductor logic families such as rapid-single-flux-quantum (RSFQ). Simulation and experimental results show that AQFP logic can achieve an energy-delay-product (EDP) near quantum limit using practical circuit parameters and available fabrication processes. To shed some light on the design automation and guidelines of AQFP circuits, in this paper we present an automatic synthesis framework for AQFP and perform synthesis on 18 circuits, including 11 ISCAS-85 circuit benchmarks, 6 deep-learning accelerator components, and a 32-bit RISC-V ALU, based on our developed standard cell library of AQFP technology. Synthesis results demonstrate the significant advantage of AQFP technology. We forecast 9,313×, 25,242× and 48,466× energy-per-operation advantage, compared to the synthesis results of TSMC (Taiwan Semiconductor Manufacturing Company) 12 nm fin field-effect transistor (FinFET), 28 nm and 40 nm complementary metal-oxide-semiconductor (CMOS) technology nodes, respectively.

DESIGN OF RELIABLE AND EFFICIENT MANCHESTER CARRY CHAIN ADDER BASED 8-BIT ALU FOR HIGH SPEED APPLICATIONS

This paper gives a detailed design and implementation of an 8-bit ALU for using Manchester carry chain adder in order to minimize the delay and power. The designed ALU is simulated using cadence virtuoso 45 nm process technology. The obtained results were compared with the existed results and its clearly indicates the proposed 8 bit ALU is more reliable and accurate with the existed architecture ,And also it occupies less area and faster

Design and analysis of low power 8-bit ALU on reversible logic for nanoprocessors

A low power reversible 8-bit ALU using single electron transistor (SET) for Nano processors is designed in this paper. Since there is a possibility in reversible logic to build circuits from many-port gates that do not destroy the capacity to store information, the basic blocks of ALU are constructed using one of the assuring many port gates called DKGP reversible gate. Then the blocks are technologically advanced to the transistor level using CMOS technology. The outputs are verified for given input frequency with the operating voltage of 5 V using SPICE simulation. It is also observed that the output glitches are obtained with low operating voltage of less than 2 V in CMOS technology. The same blocks of ALU are constructed using SET technology and the outputs are verified through simulation. The simulation results have shown that the same output response with no glitches is obtained for the same input frequency as in CMOS, with very low operating voltage of 25 mV. It is inferred that there is a drastic difference in power dissipation with SET and CMOS technology. Therefore SET technology has the potential toward the development of Nano-electronic components and can be adopted for various low power digital applications. This is the first attempt to design reversible ALU using pure SET technology from our study.

Design and analysis of high-speed 8-bit ALU using 18 nm FinFET technology

All modern computational devices consist of ALU. With increase in complexity of software and the consistent shift of software towards parallelism, high speed processors with hardware support for time consuming operations such as multiplication would benefit. Smaller, compact devices such as IoT devices need to run software such as security software and be able to offload computation cost from the cloud. In this paper, a high speed 8-bit ALU using 18 nm FinFET technology is proposed. The arithmetic and logical unit consists of fast compute units such as Kogge Stone fast adder and Dadda multiplier along with basic logic gates. In this paper, an ALU with each compute unit optimized for speed is proposed, while responsibly consuming area. Dadda multiplier is of 8 × 8 architecture as opposed to conventional approach of 4 × 4 making it a true 8-bit ALU. Simulation and analysis is done using Cadence Virtuoso in Analog Design Environment. The transistor count of proposed design is 5298, the power consumption is 219 µW and maximum delay is 166.8 ps. The design is also expected to consume a maximum of one clock cycle for any computation.