6-inch Si Substrates Research Articles

1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier

This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plate junction electric field of 2.8 MV/cm, being close to the material limit for GaN. The device also shows a high on/off ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 mΩ∙cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.

GaN quasi-vertical trench MOSFETs grown on Si substrate with ON-current exceeding 1 A

This work reports GaN quasi-vertical trench MOSFETs grown on 6-inch Si substrates. The device with single-trench design shows a specific ON-resistance of 0.84 mΩ·cm2, a maximum drain current density of 5.0 kA cm−2, and a breakdown voltage of 320 V, after fine-tuning of the channel doping and employment of a thick bottom dielectric process. The large-area (∼0.54 mm2) GaN-on-Si trench MOSFET with multiple-finger design shows an ON-current of 1.1 A, an ON-resistance of 4.0 Ω and a breakdown voltage of 205 V.

Temperature dependent lateral and vertical conduction mechanisms in AlGaN/GaN HEMT on thinned silicon substrate

This paper presents the influence of Si substrate thinning by grinding and dicing on the mechanical and electrical properties of AlGaN/GaN HEMT grown on 6-inch Si substrate. By experimentally removing 96% of the Si substrate, an increase in the lateral breakdown voltage by 13% is achieved for a wide temperature range. A decreasing vertical breakdown voltage with substrate thinning shows the necessity of substrate replacement to maintain the vertical isolation. Poole-Frenkel and space charge limited conduction mechanisms are identified for the vertical leakage in forward and reverse bias down to thicknesses of 200 μm, respectively. The increase in chip bow and the resulting increase in tensile strain in the epitaxial layers resulting from the substrate removal are correlated to a 40% decrease in 2DEG charge carrier concentration along with a 27% increase in threshold voltage. These findings are explained by strain-induced gate barrier and polarization charge variations.

Fully Vertical GaN-on-Si power MOSFETs

We report the first demonstration of fully vertical power MOSFETs on 6.6- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick GaN, grown on a 6-inch Si substrate by metal-organic chemical vapor deposition. A robust fabrication method was developed based on a selective and local removal of the Si substrate as well as the resistive GaN buffer layers, followed by a conformal deposition of a 35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick copper layer on the backside by electroplating, which provides excellent mechanical stability and electrical contact to the drain terminal. The fabrication process of the gate trench was optimized, improving considerably the effective mobility at the p-GaN channel and the output current of the devices. High-performance fully vertical GaN-on-Si MOSFETs are presented, with a low specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\textsf {on,sp}}$ </tex-math></inline-formula> ) of 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a high OFF-state breakdown voltage of 520 V. Our results reveal a major step toward the realization of high-performance GaN vertical power devices on cost-effective Si substrates.

Uniformity and repeatability of InAlN-barrier HEMTs growth by high-speed-rotation single-wafer MOCVD tool

We fabricated high-electron-mobility transistor structures with InAlN as a barrier layer on 8- or 6-inch Si substrates by using a recently developed high-speed-wafer-rotation single-wafer MOCVD tool. It has been reported that Ga inclusion in the InAlN layer causes serious problems in the control of group III metal composition in some cases, but the samples grown using the tool exhibited an InAlN layer with an abrupt interface and almost no Ga inclusion. Excellent in-wafer uniformity, repeatability, and wafer-to-wafer uniformity of device structure are also reported. The results shown in this paper indicate high performance of the tool in the real production of devices.

High-Efficiency and Crack-Free InGaN-Based LEDs on a 6-inch Si (111) Substrate With a Composite Buffer Layer Structure and Quaternary Superlattices Electron-Blocking Layers

In this paper, a composite buffer layer structure (CBLS) with multiple AlGaN layers and grading of Al composition/u-GaN1/(AlN/GaN) superlattices/u-GaN2 and InAlGaN/AlGaN quaternary superlattices electron-blocking layers (QSLs-EBLs) are introduced into the epitaxial growth of InGaN-based light-emitting diodes (LEDs) on 6-inch Si (111) substrates to suppress cracking and improve the crystalline quality and emission efficiency. The effect of CBLS and QSLs-EBL on the crystalline quality and emission efficiency of InGaN-based LEDs on Si substrates was studied in detail. Optical microscopic images revealed the absence of cracks and Ga melt-back etching. The atomic force microscopy images exhibited that the root-mean-square value of the surface morphology was only 0.82 nm. The full widths at half maxima of the (0002) and (1012) reflections in the double crystal X-ray rocking curve were ~330 and 450 respectively. The total threading dislocation density, revealed by transmission electron microscopy, was <; 6× 108 cm-2. From the material characterizations, described above, blue and white LEDs emitters were fabricated using the epiwafers of InGaN-based LEDs on 6-inch Si substrates. The blue LEDs emitter that comprised blue LEDs chip and clear lenses had an emission power of 490 mW at 350 mA, a wall-plug efficiency of 45% at 350 mA, and an efficiency droop of 80%. The white LEDs emitter that comprised blue LEDs chip and yellow phosphor had an emission efficiency of ~110 lm/W at 350 mA and an efficiency droop of 78%. These results imply that the use of a CBLS and QSLs-EBL was found to be very simple and effective in fabricating high-efficiency InGaN-based LEDs on Si for solid-state lighting applications.

Progress in the Molecular Beam Epitaxy of HgCdTe on Large-Area Si and CdZnTe Substrates

This paper presents the progress in the molecular beam epitaxy (MBE) growth of HgCdTe on large-area Si and CdZnTe substrates at Raytheon Vision Systems. We report a very high-quality HgCdTe growth, for the first time, on an 8 cm x 8 cm CdZnTe substrate. This paper also describes the excellent HgCdTe growth repeatability on multiple 7 cm x 7 cm CdZnTe substrates. In order to study the percentage wafer area yield and its consistency from run to run, small lots of dual-band long-wave infrared/long-wave infrared triple-layer heterojunction (TLHJ) layers on 5 cm x 5 cm CdZnTe substrates and single-color double-layer heterojunction (DLHJ) layers on 6-inch Si substrates were grown and tested for cutoff wavelength uniformity and micro- and macrovoid defect density and uniformity. The results show that the entire lot of 12 DLHJ-HgCdTe layers on 6-inch Si wafers meet the testing criterion of cutoff wavelength within the range 4.76 ±0.1 μm at 130 K and micro- and macrovoid defect density of≤50 cm -2 and 5 cm -2 , respectively. Likewise, five out of six dual-band TLHJ-HgCdTe layers on 5 cm x 5 cm CdZnTe substrates meet the testing criterion of cutoff wavelength within the range 6.3 ± 0.1 μm at 300 K and micro- and macrovoid defect density of ≤2000 cm -2 and 500 cm -2 , respectively, on the entire wafer area. Overall we have found that scaling our HgCdTe MBE process to a 10-inch MBE system has provided significant benefits in terms of both wafer uniformity and quality.

Growth of III-nitride photonic structures on large area silicon substrates

We report on the growth of high quality aluminum nitride (AlN) and gallium nitride (GaN) epilayers on large area (6in. diameter) silicon (111) substrates by metal organic chemical vapor deposition. We have demonstrated the feasibility of growing crack-free high quality III-nitride photonic structures and devices on 6inch Si substrates through the fabrication of blue light emitting diodes based upon nitride multiple quantum wells with high performance. The demonstration further enhances the prospects for achieving photonic integrated circuits based upon nitride-on-Si material system.

Raman Determination of Stresses and Strains in 3C-SiC Films Grown on 6-Inch Si Substrates

Raman Determination of Stresses and Strains in 3C-SiC Films Grown on 6-Inch Si Substrates