6-bit Digital Attenuator Research Articles

Wideband pHEMT Digital Attenuator With Positive Voltage Control Driver

This letter presents a wideband 6-bit digital attenuator with positive voltage driving capability. The designed attenuator solves the problem that traditional pseudomorphic high-electron-mobility transistor (pHEMT) attenuators need negative voltage control so that it can be better compatible with CMOS control signals. The frequency-select attenuation parallel (FSAP) network is utilized to improve high-frequency attenuation fluctuation and enable wideband flat attenuation characteristics. Simultaneously, this letter creatively proposed the lossy dc-block (LDB) network, which not only completes the dc blocking effect but also improves the low-frequency resonance in high attenuation state. The attenuator is implemented in the GaAs 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pHEMT process. It demonstrates a 31.5-dB attenuation range with an increment of 0.5 dB. In the range of 0.05–6 GHz, the measured results showed that the root-mean-square (rms) attenuation and the phase error are within 0.8 dB and 16°, respectively, the reference state insertion loss (IL) is better than 2.3 dB, and the return loss is better than 15 dB for all the 64 attenuation states; the total chip size is 2 mm2.

A 7.5–9 GHz GaAs Two-Channel Multi-Function Chip

Based on the 0.5 μm GaAs enhancement/depletion (E/D) Pseudomorphic High Electron Mobility Transistor (pHEMT) process, a 7.5–9 GHz two-channel amplitude phase control multi-function chip (MFC) was developed successfully. The chip was integrated with a 6-bit digital phase shifter, a 6-bit digital attenuator, and a single pole single throw (SPST) switch in each channel. A design for the absorptive SPST switch is deployed to optimize the return loss and control channel array calibration. In the 8 dB and 16 dB attenuation bit, a switched-path-type topology is employed in order to obtain a good flatness of attenuation characteristic and achieve low additive phase shift. A 27-bit serial-to-parallel converter (SPC) was introduced to decrease the control lines and pads of the chip, and the power consumption was less than 70 mW. The measurement result shows that the insertion loss is less than −13 dB and the return loss is better than −19 dB. In both channels, the 64-state root mean square (RMS) errors of the phase shifter is less than 2° and the RMS parasitic amplitude error is less than 0.2 dB. The RMS attenuation error is less than 0.45 dB and the RMS parasitic phase error is less than 2.4°. The size of the chip is 3.5 mm × 4.5 mm.

A millimeter-wave 6-bit digital attenuator with high accuracy and low insertion loss

A millimeter-wave 6-bit digital attenuator with high accuracy and low insertion loss

능동 위상 배열 SAR 안테나를 위한 X-대역 송수신 모듈의 설계 및 제작

본 논문에서는 능동 위상 배열 안테나를 가지는 SAR(Synthetic Aperture Radar)용 X-대역 T/R(Transmit/Receive) 모듈을 설계, 제작하였다. T/R 모듈은 X-대역에서 800 MHz 이상 대역폭을 가지며 이중 편파 운용이 가능하다. 송신 출력 7 W 이상에 잡음지수 3.9 dB 이하를 가진다. 위상과 이득은 6비트 위상변위기와 6비트 디지털 감쇠기에 의해 각각 제어된다. 게다가 제작된 T/R 모듈은 방향성 결합기와 전력분배기로 연결되는 성능 점검/보정 포트를 가진다. LTCC 다층 기판을 사용하여 고직접화 T/R 모듈이 가능하게 하였다. 모든 동작 주파수 대역에서 수신시 RMS 이득 오차는 최대 0.8 dB 이하이고, 송/수신시 RMS 위상 오차는 최대 <TEX>$4^{\circ}$</TEX> 이하로 측정되었고, 또한 시험 결과 T/R 모듈은 요구되는 전기적인 성능을 만족하였다. 이 구조는 능동 위상 배열 SAR용 안테나에 적용될 수 있음을 확인하였다. In this paper, a X-Band T/R-module for SAR(Synthetic Aperture Radar) systems based on active phased array antennas is designed and fabricated. The T/R modules have a and width of more than 800 MHz centered at X-Band and support dual, switched polarizations. The output power of the module is 7 watts over a wide bandwidth. The noise figure is as low as 3.9 dB. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit digital attenuator, respectively. Further the fabricated T/R module has est and calibration port with directional coupler and power divider. Highly integrated T/R module is achieved by using LTCC(Low Temperature Co-fired Ceramic) multiple layer substrate. RMS gain error is less than 0.8 dB max. in Rx mode, and RMS phase error is less than <TEX>$4^{\circ}$</TEX> max. in Rx/Tx phase under all operating frequency band, or the T/R module meet the required electrical performance m test. This structure an be applied to active phase array SAR Antennas.

Design and Implementation of SPDT Switch, 6 Bit Digital Attenuator, 6 bit Digital Phase Shifter For L-Band T/R Module Using 0.7μm GaAs MMIC Technology

The performance of modern radar systems with active phased array antennas is mainly driven by the performance of the microwave T/R modules. To reduce the size, weight, cost and power consumption, as well as to achieve better phase and amplitude accuracies for realizing low side lobe levels with an accurate beam steering, T/R modules, now-a-days, employ MMICs (Monolithic Microwave Integrated Circuits) for implementing Transmit/ Receive chain.The L-band SPDT Switch, 6-Bit Digital Attenuator, 6-Bit Digital Phase Shifter have been designed using GAETEC Hyderabad 0.7μm GaAs MESFET Switch model to handle 30dBm peak power. All the above components have been designed and simulated using Agilent ADS CAD tool interfaced with Academy Layout.The SPDT Switch with insertion loss less than -1dB, isolation greater than 60dB and return loss better than 20dB has been realized on a single 3.0 mm × 2.35 mm GaAs chip. A 6-Bit Digital Attenuator has a 31.5dB attenuation range in 0.5dB increments, 2.5° phase error and return loss better than 15dB. The 6 bits are cascaded to form a complete attenuator on a double 3.5 mm × 2.35 mm GaAs chip with 3 attenuator bits in each for a better yield. A 6-Bit Digital Phase Shifter with 9dB insertion loss, return loss better than 15 dB has been realized on a two GaAs chips with size 4.0mm × 2.35mm and 3.0 mm × 2.35 mm and 3 phase bits in each chip for the better yield.