4H-SiC Trench Gate MOSFETs Research Articles

Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance

Novel 1.7-kV 4H-SiC trench-gate MOSFETs (TMOSFETs) with a grid pattern and a smaller specific on-resistance are proposed and demonstrated via numerical simulations. The proposed TMOSFETs provide a reduced cell pitch compared with TMOSFETs with square and stripe patterns. Although TMOSFETs with a grid pattern reduce the channel area by approximately 10%, the cell density is increased by approximately 35%. Consequently, the specific on-resistance of the grid pattern is less than that of the square and stripe patterns. The forward blocking characteristics of the grid pattern are increased by the reduced impact ionization rate at the P/N junction. As a result, the figure-of-merit (FOM) of the grid pattern is increased by approximately 33%.

Investigation of a 4H-SiC Trench MOSFET with Back-Side Super Junction.

In this paper, a 4H-SiC trench gate MOSFET, featuring a super junction layer located on the drain-region side, is presented to enhance the breakdown voltage and the figures of merit (FOM). The proposed structure is investigated and compared with the conventional structure with a 2D numerical simulator—ATLAS. The investigation results have demonstrated that the breakdown voltage in the proposed structure is enhanced by 21.2%, and the FOM is improved by 39.6%. In addition, the proposed structure has an increased short-circuit capability.

Analysis of Electrical Characteristics in 4H-SiC Trench-Gate MOSFETs with Grounded Bottom Protection p-Well Using Analytical Modeling

A new analytical model to analyze and optimize the electrical characteristics of 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors (TMOSFETs) with a grounded bottom protection p-well (BPW) was proposed. The optimal BPW doping concentration (NBPW) was extracted by analytical modeling and a numerical technology computer-aided design (TCAD) simulation, in order to analyze the breakdown mechanisms for SiC TMOSFETs using BPW, while considering the electric field distribution at the edge of the trench gate. Our results showed that the optimal NBPW obtained by analytical modeling was almost identical to the simulation results. In addition, the reverse transfer capacitance (Cgd) values obtained from the analytical model correspond with the results of the TCAD simulation by approximately 86%; therefore, this model can predict the switching characteristics of the effect BPW regions.

Inverse Modeling of 4H-SiC Trench Gate MOSFETs Validated with Electrical and Physical Characterization

The effective modeling methodology of 4H-SiC trench gate MOSFETs is presented. The potential barrier lowering at the MOS channel region suggested by I-V measurements is implemented to commercial TCAD tool as the net-doping reduction. The proposed model is validated by comparison of TCAD simulations with I-V measurements and SEM image observations.

An Improved 4H-SiC Trench Gate MOSFETs Structure with Low On-Resistance and Reduced Gate Charge

In this paper, an improved 4H-SiC trench-gate metal-oxide-semiconductor field effect transistors (UMOSFETs) structure with low on-resistance and reduced gate charge is proposed. The added n-type region in the improved structure reduces on-resistance of the device significantly while maintaining same breakdown voltage. The gate of the improved structure is designed as a p-n junction to reduce the gate-charge. The specific on-resistances of the improved 4H-SiC UMOSFETs is 1.87 mΩ.cm2 at VGS=18 V and VDS=10 V, compared with 4.48 mΩ.cm2 for the conventional p+ shielding UMOSFETs structure with same breakdown voltage. The on-resistance and figure of merit (FOM = VBR2/Ron) improve by 58.3% and 103.6%, respectively. Compared with the conventional structure, the results show that gate-drain charge of the improved structure can be improved by 23.8%.

Self-aligned formation of the trench bottom shielding region in 4H-SiC trench gate MOSFET

To suppress the electric field in the gate oxide in a trench gate MOSFET (UMOSFET) with small cell pitch, we developed a technique to form the p+ region using self-aligned ion implantation under the gate trench. To prevent Al+ injection into the trench sidewalls, conditions of thin oxide layer deposition and Al+ implantation were optimized by process simulation. The resulting SiC trench MOS capacitors exhibited long-term reliability, with no degradation in lifetime by the p+ shielding region, and a specific on-resistance of 9.4 mΩ cm2 with a blocking voltage of 3800 V was achieved in the UMOSFET.

4H-SiC trench gate MOSFETs with field plate termination

Field plate (FP)-terminated 4H-SiC trench gate MOSFETs are demonstrated in this work. N+/P−/N−/N+ multiple epitaxial layers were grown on 3-inch N+ type 4H-SiC substrate by chemical vapor deposition (CVD), and then the 4H-SiC trench gate MOSFETs were fabricated based on the standard trench transistor fabrication. Current-voltage measurements in forward and reverse bias have been performed on different devices with and without FP protections. It is found that more than 60% of the devices protected with FP termination are able to block 850 V. The measurements also show that the devices have the small leakage currents 0.15 nA at 600 V and 2.5 nA at 800 V, respectively. The experimental results also were compared with the simulated results, which show good agreement with each other in the trend. The limited performance of the devices is mainly because of the damage induced on the trench sidewalls from the etching process and the quality of the SiO2 films. Therefore, the 4H-SiC trench gate MOSFETs are expected to be optimized by reducing the etching damage and growing high-quality SiO2 dielectric films.