4H-SiC Metal Oxide Semiconductor Research Articles

Photon-assisted electron depopulation of 4H-SiC/SiO2 interface states in n-channel 4H-SiC metal–oxide–semiconductor field effect transistors

4H-SiC/SiO2 interface states play a major role in the performance and reliability of modern 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). To gain new insights into these interface states, we developed a cryogenic measurement technique that uses photon-assisted electron depopulation to probe device performance limiting 4H-SiC/SiO2 interface states. This technique enables the characterization of shallow as well as deep states at the 4H-SiC/SiO2 interface of fully processed devices using a cryogenic probe station. Our method is performed on n-channel 4H-SiC MOSFET test structures with deposited oxide and postoxidation anneal. We identify conditions under which the electrons remain trapped at 4H-SiC/SiO2 interface states and trigger the controlled photon-assisted electron depopulation within a range of photon energies. This allows us to prove the presence of near interface traps, which have previously been found in thermally grown 4H-SiC MOS structures. Our results are supported by device simulations. Additionally, we study the impact of irradiation intensity and light exposure time on the photon-induced processes.

Factors Affecting Bias Temperature Instability in 4H-SiC MOS Capacitors

The threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) show instability during normal operation, especially after bias temperature stress (BTS), and this phenomenon is called bias temperature instability (BTI). In this work, to study the factors affecting threshold voltage (Vth) instability of SiC MOSFETs, flat-band voltage (Vfb) instability of 4H-SiC metal-oxide-semiconductor (MOS) capacitors is discussed instead. Some factors, including the polarity of gate bias stress, stress time, and stress temperature, are analyzed by performing one-way bias stress C-V measurements in the devices. Firstly, positive bias stress leads to a positive Vfb shift, and negative bias stress leads to a negative one. Moreover, the Vfb shift appears to exhibit a linear relationship with log (stress time). Furthermore, the Vfb shift decreases over the temperature range of 225 K to 400 K, but slightly increases at 475 K. Finally, the Vfb stability of the MOS devices fabricated by 1200 °C NO post-oxidation annealing (POA) and those fabricated by 1250 °C NO POA is similar.

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.

Origin of trap assisted tunnelling in ammonia annealed SiC trench MOSFETs

The interface between silicon carbide (SiC) and silicon dioxide (SiO2) is of considerable importance for the performance and reliability of 4H-SiC (trench) metal oxide semiconductor field effect transistors (MOSFETs) and various different post oxidation anneals (POAs) have been used to optimize its quality. Whereas nitric oxide (NO) POA leads to very reliable and well performing MOSFETs, ammonia (NH3) can further improve the device performance, however, at the cost of the gate oxide (GOX) reliability, e.g. leading to trap assisted tunneling (TAT). We investigate the origin of TAT and GOX leakage in differently annealed gate oxides experimentally, using 4H-SiC trench MOSFETs, and theoretically, using Density Functional Theory (DFT) simulations. Our findings reinforce the view that the NO anneal for SiC devices results in the best overall quality as devices annealed in NH3 and nitrogen N2 show higher oxide charge density and leakage currents. DFT simulations demonstrate that, contrary to what has often been assumed so far, NH3 annealing leads to the formation of additional hydrogen related defects, which open leakage paths in the oxide otherwise not present in NO treated oxides.

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field () on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be and , respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of in controlling the value of channel mobility in 4H-SiC MOSFETs.

Detection of near-interface traps in NO annealed 4H-SiC metal oxide semiconductor capacitors combining different electrical characterization methods

Fast near-interface (NI) traps have recently been suggested to be the main cause for poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors. Combining capacitance, conductance, and thermal dielectric relaxation current (TDRC) analysis at low temperatures of nitrided SiC MOS capacitors, we observe two categories of fast and slow near-interface traps at the SiO2/4H-SiC interface. TDRC reveals a suppression of slow near-interface traps after nitridation. Capacitance and conductance analysis reveals a high density of fast NI traps close to the SiC conduction band edge that are enhanced by nitridation. The very fast response of NI traps prevents them from detection using TDRC or deep level transient spectroscopy.

Electrical detection of TV2a-type silicon vacancy spin defect in 4H-SiC MOSFETs

Color centers in silicon carbide (4H-SiC) are potentially usable as spin defects for quantum sensing and quantum information technology. In particular, neutral divacancies (the P6/P7centers, VSiVC0) and a certain type of silicon vacancies (the TV2a center, VSi- at the k site) are promising for addressing and manipulating single spins. Although the TV2a spin is readable at room temperature, the readout techniques have been limited to luminescence-based ones (e.g., optically detected magnetic resonance). In this study, we demonstrated electrical detection of TV2a-type silicon vacancies at room temperature by using electrically detected magnetic resonance on 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). TV2a spin defects were embedded in the channel region of well-defined 4H-SiC MOSFETs via controlled proton irradiation. The number of detected TV2a spins was estimated to be ∼105. We also found that the charge state of the TV2a spin defect can be controlled by varying the gate voltage applied to the MOSFET.

High temperature characteristics of nitric oxide annealed p-channel 4H-SiC metal oxide semiconductor field effect transistors

In this work, p-channel 4H-SiC MOSFETs were fabricated and analyzed at high temperature. It is demonstrated that nitridation of the gate oxide enables enhancement mode operation in these devices. Nitrogen incorporation at the 4H-SiC/SiO2 interface by nitric oxide annealing reduces the interface trap density energetically located in the lower half of the 4H-SiC bandgap, resulting in viable high temperature p-channel devices. In the 27–300 °C temperature range, the threshold voltage decreases with increasing temperature, consistent with the reduction of occupied interface traps at higher temperatures. The hole channel mobility is weakly temperature dependent under strong inversion conditions. Hall measurements support that above the threshold voltage, the mobility is limited by surface roughness scattering. In weaker inversion, the channel conductivity is limited by interface hole trapping and Coulomb scattering. In addition, high temperature bias stress measurements confirm a temperature activated hole trapping under negative gate bias, which requires further investigations.

Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to a positive gate stress bias. Experimental analysis of the threshold voltage transients indicates that both electron and hole trappings take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing–decreasing–increasing pattern. At low/moderate stress fields (<7 MV/cm), the electron trapping kinetics responsible for a positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, which explains the logarithmic degradation kinetics. In the high field regime (>8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field, and generate holes through impact ionization (II) or anode hole injection. These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.

Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs* *Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0903203), the National Natural Science Foundation of China (Grant No. 62004033), and China Postdoctoral Science Foundation (Grant No. 2020M683287).

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (ΔV th,sub) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger ΔV th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of ΔV th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious ΔV th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level (E i) and valence band (E v). The maximum ΔV th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states (D it) between E i and E v. These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of ΔV th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.

Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature N₂ Annealing

Effects of high-temperature (1400 °C–1600 °C) N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing on the interface states of 4H- SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the channel mobility of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) were investigated. It is demonstrated that high-temperature N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing is effective not only for the reduction of the interface state density near the conduction band edge but also for that near the valence band edge. N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing improves channel mobility of both n- and p-channel MOSFETs as in the case of nitric oxide (NO) annealing. In particular, the field-effect mobility of the p-channel MOSFETs annealed in an N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient was improved to 17 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, which is 30% higher than that of NO-annealed MOSFETs. The interface state density estimated from the subthreshold slopes in the MOSFETs is much higher than that extracted by the high–low method but is almost comparable to that estimated by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\psi _{\text {s}}$ </tex-math></inline-formula> method in both the cases of interface states near the conduction and the valence band edges. These results suggest that there exist fast states (>1 MHz) near the valence band edge, and these fast states affect the channel mobilities of p-channel SiC MOSFETs as in the case of n-channel MOSFETs.

Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N&lt;sub&gt;2&lt;/sub&gt; Annealing with Conductance Measurements

We have determined, using the Conductance-Frequency (G-ω) Technique, the creation and annihilation process of the 3 interface trap levels (OX, OX’ and NI levels) previously reported [1-3] and their possible correlation to inversion electron trapping and mobilities. The measurements were carried out on various 4H-SiC Metal Oxide Semiconductor (MOS) capacitors that have been processed using several gate oxide processes [2,5,6]. Our analysis focus on the correlation of the interface trap levels on the process conditions so as to first understand and then control their formation.

Synergistic passivation effects of nitrogen plasma and oxygen plasma on improving the interface quality and bias temperature instability of 4H-SiC MOS capacitors

Interface properties and bias temperature instability (BTI) determine the performance and stability of SiC metal-oxide semiconductor (MOS) devices. In this work, we propose an electron cyclotron resonance microwave nitrogen–oxygen (NO) mixed plasma post-oxidation annealing (POA) process to improve the interface properties and BTI of 4H-SiC MOS capacitors. Results showed that the NO mixed plasma POA reduces the density of interface traps, maintains the stability of the flat band voltage (Vfb) hysteresis under four successive cycles of positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) at 423 K, and significantly reduces the Vfb hysteresis under alternating PBTS and NBTS at 100 K. The oxide traps remarkably decreased to 2.27 × 1012 cm−2 after NO mixed plasma POA. The related passivation and improvement mechanisms were further studied by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, and density functional theory calculations. The synergistic effects of highly reactive N and O plasma promoted the considerable absorption of N at the interface and prevented further oxidation of the SiC substrate. We also elaborate on the effects of N, O, and NO plasma on the elimination and passivation of O vacancy defects, C-related defects (SiOxCy and C dimer), and Si interstitial defects and discuss implications of the simultaneous suppression of electron and hole trapping.

Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

Bias temperature stresses (BTSs) are critical factors that cause severe threshold voltage (Vth) instability in silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this work, we studied the behavior of flatband voltage (Vfb) instability in 4H-SiC MOS capacitors under various BTSs from low temperature (LT) to high temperature (HT) considering the combined effects of interfacial traps and mobile ions. Results showed that nitrogen and nitrogen–hydrogen plasma passivation improved the Vfb instability. The initial sweeping gate voltage determined the direction of Vfb shift. BTSs from LT to HT induced different capacitance–voltage hysteresis characteristics. The Vfb shift was further separated according to the contribution of the interface trapped, oxide trapped, and mobile ionic charges. At LT, the charge trapping dominated the shift behavior. The interface trap density was also extracted by another high-frequency and quasi-static method, which was the same as the separated interface trap density at 100 K, confirming the separation correctness of Vfb shift. At room temperature, charge trapping and mobile ions with very weak mobility contributed to the Vfb shift. At HT, mobile ions that counteracted the charge-trapping effect determined the Vfb shift, although the additional traps were activated in the interface and oxide. Physical models of Vfb instability under different temperature stresses were proposed. Finally, we chose the 100 K, 273 K, and 423 K to analyze gate bias stresses and stress time induced Vfb instabilities as well as their mechanisms.

Interface properties and bias temperature instability with ternary H–Cl–N mixed plasma post-oxidation annealing in 4H–SiC MOS capacitors

Abstract Interface properties and bias temperature instability (BTI) are the two critical issues that severely restricted the performance and reliability of SiC metal-oxide-semiconductor (MOS) devices. In this work, we simultaneously improved interface properties and BTI in 4H–SiC MOS capacitors by modifying SiC/SiO2 interface via ternary H–Cl–N mixed plasma post-oxidation annealing (POA). Results showed that H–Cl–N mixed plasma POA improved the oxide insulating properties, reduced density of interface traps, and improved the BTI both at low temperature and high temperature. The modification of interface was achieved by enriching H, Cl, and N elements at and near the interface, which not only led to a smoother interface, but also could bond with interfacial traps. The synergistic effects of H, Cl, and N in reducing traps at and near the interface were due to the conversion of the trap levels to or outside the lower half of the SiC bandgap, thereby suppressing electron trapping. Density Functional Theory calculations further indicated that the Cl and N could passivate mobile ions and Si-Si bonds. N passivation and combined N and H passivation were stable and effective in passivating Si-Si bonds and reducing oxygen vacancies.

Evaluation of interface trap characterization methods in 4H-SiC metal oxide semiconductor structures over a wide temperature range

In this paper, four widely used interface trap characterization methods based on quasistatic and high-frequency capacitance–voltage (CV) and conductance–frequency (Gω) measurements are evaluated at thermally oxidized 4H-SiC metal oxide semiconductor structures. To cover a wide range of defect levels in a wide bandgap semiconductor, the CV and Gω measurements are conducted at temperatures ranging from 150 to 600 K. Interface trap densities Dit are extracted using the high-frequency Terman method, the low frequency capacitance method, the high-low frequency method, and the conductance method. A very good agreement between the different methods is observed in restricted energy ranges. The use of the conductance method allowed for the determination of defect states in an energy range of almost 800 meV. A strong hysteresis of bidirectional CV curves is observed at different temperatures and is used to estimate border trap densities. The presence of mobile charges in the oxide is found to be a limiting factor for high temperature CV measurements. Low temperature Gω measurements revealed a second conductance peak which is identified as the 100 meV nitrogen donor level.

Effects of nitrogen on the interface density of states distribution in 4H-SiC metal oxide semiconductor field effect transistors: Super-hyperfine interactions and near interface silicon vacancy energy levels

The performance of silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is greatly enhanced by a post-oxidation anneal in NO. These anneals greatly improve effective channel mobilities and substantially decrease interface trap densities. In this work, we investigate the effect of NO anneals on the interface density of states through density functional theory (DFT) calculations and electrically detected magnetic resonance (EDMR) measurements. EDMR measurements on 4H-silicon carbide (4H-SiC) MOSFETs indicate that NO annealing substantially reduces the density of near interface SiC silicon vacancy centers: it results in a 30-fold reduction in the EDMR amplitude. The anneal also alters post-NO anneal resonance line shapes significantly. EDMR measurements exclusively sensitive to interface traps with near midgap energy levels have line shapes relatively unaffected by NO anneals, whereas the measurements sensitive to defects with energy levels more broadly distributed in the 4H-SiC bandgap are significantly altered by the anneals. Using DFT, we show that the observed change in EDMR linewidth and the correlation with energy levels can be explained by nitrogen atoms introduced by the NO annealing substituting into nearby carbon sites of silicon vacancy defects.

Hall effect mobility for SiC MOSFETs with increasing dose of nitrogen implantation into channel region

The Hall effect mobility (μHall) of the Si-face 4H-SiC metal–oxide–semiconductor field effect transistor (MOSFET) with a nitrogen (N)-implanted channel region was investigated by increasing the N dose. The μHall in the channel region was systematically examined regarding channel structures, that is, the surface and buried channels. It was experimentally demonstrated that increasing the N dose results in an improvement in μHall in the channel region due to the formation of the buried channel. However, further increase in N dose was found to decrease the μHall in the channel region, owing to the decrease in the electron mobility in the N-implanted bulk region.

Improvement of Threshold Voltage Reliability of 4H-SiC MOSFETs With Lanthanum Silicate by High Temperature Forming Gas Anneal

We report the effect of a high-temperature forming gas anneal (FGA) on the electrical characteristics and threshold voltage (VT) instability of high-mobility Si-face (0001) 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) with lanthanum silicate (LaSiOx). The MOSFET with LaSiOx after 800 °C FGA in 5% H2 and 95% N2 mixture shows significantly reduced VT shift under 3-MV/cm positive bias stressing from 2.78 to 1.65 V, while maintaining high field-effect mobility of 122.7 cm2/Vs and sufficiently positive VT of 2.76 V.

Electrical characterization of 4H-SiC metal–oxide–semiconductor structure with Al2O3 stacking layers as dielectric

Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10−10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV−1 cm−2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics.