4H-SiC Metal-oxide-semiconductor Field-effect Transistors Research Articles

Simulation of Threshold Voltage Instability of 4H-SiC MOSFET

The reliability issue of threshold voltage (Vgs(th)) still exists in Silicon carbide (SiC) based metal-oxide-semiconductor-field-effect-transistors (MOSFETs). In this paper, the threshold voltage instability of 4H-SiC MOSFET is deeply studied through Silvaco TCAD simulation. This work mainly investigates the instability (shift) of the Vgs(th) affected by interface states (interface traps), near interface traps, and mobile ions. The results display that the effect of near interface traps on the Vgs(th) shift is greater than that of interface traps. The electron capture ability is related to the energy level of the traps. With the energy level increasing, the Vgs(th) shift increases firstly and then decreases. The peak energy level is related to the trap position and trap density. Furthermore, the effect of the mobile ions in the oxide layer on the Vgs(th) shift is limited. However, when moving to the SiC/SiO2 interface, they will greatly impact the Vgs(th) and affect the device performance seriously.

Improvement of channel-carrier mobility in 4H-SiC MOSFETs correlated with passivation of very fast interface traps using sodium enhanced oxidation

Very fast interface traps have recently been suggested to be the main cause behind the rather poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Using capacitance voltage analysis and conductance spectroscopy on metal oxide semiconductor capacitors, at cryogenic temperatures, we find that these fast traps are absent in oxides made by sodium enhanced oxidation, and high inversion channel-carrier mobility in MOSFETs made by sodium enhanced oxidation is observed.

Impact of low-dose radiation on nitrided lateral 4H-SiC MOSFETs and the related mechanisms

Lateral type n-channel 4H-SiC metal--oxide--semiconductor field effect transistors (MOSFETs), fabricated using a current industrial process, are irradiated with gamma rays at different irradiation doses in this paper to carry out a profound study on the generation mechanism of radiation-induced interface traps and oxide trapped charges. Electrical parameters (e.g., threshold voltage, subthreshold swing and channel mobility) of the device before and after irradiation are investigated, and the influence of the channel orientation ( and ) on the radiation effect is discussed for the first time. A positive threshold voltage shift is observed at very low irradiation doses (< 100 krad (Si)); the threshold voltage then shifts negatively as the dose increases. It is found that the dependence of interface trap generation on the radiation dose is not the same for doses below and above 100 krad. For irradiation doses < 100 krad, the radiation-induced interface traps with relatively high generation speeds dominate the competition with radiation-induced oxide trapped charges, contributing to the positive threshold voltage shift correspondingly. All these results provide additional insight into the radiation-induced charge trapping mechanism in the SiO2/SiC interface.

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect.

Nitrogen Annealing As a Sustainable Method for Interface Trap Passivation in 4H-SiC Mosfets

Silicon Carbide (4H-SiC) has emerged as a leading wide band gap semiconductor for high-power, high-temperature applications1. 4H-SiC metal-oxide semiconductor-field-effect transistors (MOSFETs) have lower power dissipation compared to silicon, allowing for low-noise and high-efficiency all-electric vehicle drives, fast-charging stations, solar inverters, and more. While these devices provide substantial advancements for next-generation energy efficient power systems, 4H-SiC may also offer additional functionality in the form of integrated circuits (ICs) at high temperatures (>300 °C). Because of its high noise immunity and low static power consumption, lateral complementary-metal-oxide-semiconductor (CMOS) IC technology in 4H-SiC is desirable for large-scale integration2. This technology necessitates the use of both n- and p-channel MOSFETs that can operate at high temperatures.Despite the advances of 4H-SiC MOSFETs, the high density of interface states (Dit) at the 4H-SiC/SiO2 interface prevents reaching full potential resulting in high channel resistance and low mobility. Alternatives to nitric oxide (NO) annealing, the most common method adopted to reduce Dit in 4H-SiC3,4, are actively sought due to its toxicity and relatively expensive cost. Annealing in pure nitrogen (N2)5,6 at high temperatures (1400 °C-1600 °C) has been recently demonstrated promising results for 4H-SiC MOSFET processing. In this work, we report Dit measurements consistent with [6] and attempt to correlate the nitrogen areal densities of the near interfacial regions with the Dit for high temperature N2 annealing processes compared to NO. In our study, metal oxide semiconductor capacitors were fabricated on p- and n-type 4H-SiC epitaxial layers. Gate oxides were thermally grown at 1150 °C for 10 h in dry O2 resulting in a ~ 60 nm thick oxide layer. Selected samples are then annealed in flowing N2 at high temperatures (1400 °C, 1 h; 1450 °C, 1 h; and 1500 °C, 30 minutes or 1 h) or NO (1175 °C, 2 h). X-ray photoelectron spectroscopy (XPS), carried out after etching the oxide, indicates that the amount of nitrogen at the interface due to high temperature N2 annealing is ~ 4 × higher than NO annealed devices. Simultaneous high frequency (100 kHz)- low frequency CV was performed to extract interface trap densities (Dit) for each process and compared at room temperature (27 °C) with reference 1175 °C, 2 h NO annealed samples. The comparison reveals that, N2 annealing at 1500 °C for 30 minutes with a flow rate of 3 LPM results in Dit values comparable to NO annealing across the bandgap. Moreover, nitrogen annealing is more effective in reducing Dit near the valence band than NO annealing, while the opposite is true close to the conduction band-edge, consistent with previous reports [6] and observed in atomistic models of these interfaces using the density functional theory7. Nitrogen annealing also decreases the positive fixed charges at the interface of p-type 4H-SiC and SiO2, as evidenced from the flat band voltage comparison. The oxide breakdown voltage for the devices made with 1500 °C N2 annealing was similar to that of NO annealed devices. XPS analysis of the N2 annealed devices, their behavior under high temperature and bias, and their potential to substitute NO will be further discussed.The authors gratefully acknowledge the support from the National Renewable Energy Laboratory/ US Department of Energy sub-contract NREL-AHL-9-92362-01.

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis.

The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field () on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be and , respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of in controlling the value of channel mobility in 4H-SiC MOSFETs.

Electrical detection of TV2a-type silicon vacancy spin defect in 4H-SiC MOSFETs

Color centers in silicon carbide (4H-SiC) are potentially usable as spin defects for quantum sensing and quantum information technology. In particular, neutral divacancies (the P6/P7centers, VSiVC0) and a certain type of silicon vacancies (the TV2a center, VSi- at the k site) are promising for addressing and manipulating single spins. Although the TV2a spin is readable at room temperature, the readout techniques have been limited to luminescence-based ones (e.g., optically detected magnetic resonance). In this study, we demonstrated electrical detection of TV2a-type silicon vacancies at room temperature by using electrically detected magnetic resonance on 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). TV2a spin defects were embedded in the channel region of well-defined 4H-SiC MOSFETs via controlled proton irradiation. The number of detected TV2a spins was estimated to be ∼105. We also found that the charge state of the TV2a spin defect can be controlled by varying the gate voltage applied to the MOSFET.

Impact of oxide/4H-SiC interface state density on field-effect mobility of counter-doped n-channel 4H-SiC MOSFETs

We investigated the effect of interface state density on the field-effect mobility (μ FE) of 4H-SiC counter-doped metal-oxide-semiconductor field-effect transistors (MOSFETs). We fabricated counter-doped MOSFETs with three types of gate oxides i.e. SiO2, Al2O3 formed via atomic layer deposition, and Al2O3 formed via metal layer oxidation (MLO). A maximum μ FE of 80 cm2 V−1 s−1 was obtained for the MLO-Al2O3 FET, which was 60% larger than that of the SiO2 FET. In addition, we evaluated the electron mobility in the neutral channel (μ neutral) and the rate of increase in the free electron density in the neutral channel with respect to the gate voltage (dN neutral/dV G), which are factors determining μ FE. μ neutral depended only on the channel depth, independent of the type of gate oxide. In addition, dN neutral/dV G was significantly low in the SiO2 FET because of carrier trapping at the high density of interface states, whereas this effect was smaller in the Al2O3 FETs.

Comparative Study of Hall Effect Mobility in Inversion Layer of 4H-SiC MOSFETs With Nitrided and Phosphorus-Doped Gate Oxides

In this study, the inversion layer mobility characteristics in Si-face 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with nitrided and phosphorus-doped gate oxides were compared using Hall effect measurements. The inversion layer mobility was evaluated by applying a body bias and changing the temperature. The carrier scattering properties were determined for elevated temperatures (i.e., 473 K), at which point the impact of Coulomb scattering decreases and that of phonon scattering increases. The phonon-limited mobility of these MOSFETs was almost the same when plotted as a function of the effective normal electric field in the inversion layer, possibly representing the nature of the thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiC interface. On the basis of this finding, the effect of phonon scattering was separated from the inversion layer mobility. The MOSFETs exhibited a remarkable difference in Coulomb scattering: the MOSFETs with phosphorus-doped gate oxide exhibited a more rapid increase in Coulomb-limited mobility with increasing surface carrier density than did the MOSFETs with nitride gate oxide. This resulted from the effective suppression of Coulomb scattering in the inversion layer, which is one of the reasons why phosphorus-doped gate oxide achieves higher inversion layer mobility than nitrided gate oxide. These results show that the inversion layer mobility of SiC MOSFETs can be modeled using a conventional framework of phonon, Coulomb, and surface roughness scattering. Therefore, the suppression of Coulomb scattering is key to further improving the inversion layer mobility of SiC MOSFETs.

Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications

4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.

Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to a positive gate stress bias. Experimental analysis of the threshold voltage transients indicates that both electron and hole trappings take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing–decreasing–increasing pattern. At low/moderate stress fields (&amp;lt;7 MV/cm), the electron trapping kinetics responsible for a positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, which explains the logarithmic degradation kinetics. In the high field regime (&amp;gt;8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field, and generate holes through impact ionization (II) or anode hole injection. These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

The phenomenon of reduced energy capability of power metal-oxide-semiconductor field-effect transistors (MOSFETs) at high avalanche currents is investigated in commercial 1.2-kV 4H-SiC MOSFETs. Unclamped inductive switching (UIS) measurements as well as electrical transport simulations are used to identify the current paths and maximum avalanche currents, providing insight into the design limits. The investigated devices show a reduced energy capability for avalanche current above 52 A due to the latching of the parasitic bipolar junction transistor (BJT). The BJT also limits the maximum switchable current to ≤102 A. Based on the measurements and simulations, a procedure utilizing UIS measurements for identification of design limits is presented.

The spatial and energy distribution of oxide trap responsible for 1/f noise in 4H-SiC MOSFETs

Low-frequency noise is one of the important characteristics of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) that is susceptible to oxide traps. Drain-source voltage noise models of 4H-SiC MOSFETs under low–drain-voltage and inverse condition were proposed by considering the spatial and energy non-uniform distribution of the oxide trap, based on the McWhoter model for uniform trap distribution. This study performed noise experiments on commercial 4H-SiC MOSFETs, and revealed that the non-uniform spatial and non-uniform energy distribution caused new 1/f noise phenomenon, different from that under uniform spatial and energy distribution. By combining experimental data and theoretical models, the spatial and energy distribution of oxide traps of these samples were determined.

Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of H2 etching, SiO2 deposition, and interface nitridation

4H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) and MOS capacitors were fabricated by the following procedures: H2 etching, SiO2 deposition, and nitridation, and their electrical characteristics were evaluated. Substantially low interface state densities (4–6 × 1010 cm−2 eV−1) and high channel mobilities (80–85 cm2 V−1 s−1) were achieved by N2 annealing or NO annealing after H2 etching and SiO2 deposition. The threshold voltage of the MOSFETs fabricated with N2 annealing was shifted negatively when the oxide was formed by deposition. On the other hand, normally-off operation and high channel mobility were compatible for the MOSFETs fabricated with NO annealing.

A technique to measure spin-dependent trapping events at the metal–oxide–semiconductor field-effect transistor interface: Near zero field spin-dependent charge pumping

We discuss a new technique to measure spin-dependent trapping events at the metal–oxide–semiconductor field-effect transistor (MOSFET) channel/gate dielectric interface. We call this technique near zero field spin-dependent charge pumping (NZF SDCP). It is based on a powerful MOSFET interface trap characterization measurement called charge pumping and related to an electrically detected magnetic resonance (EDMR) technique called SDCP. NZF SDCP and EDMR SDCP measurements are made on 4H-SiC MOSFETs, and we find that the introduction of nitrogen to the MOSFET interface can have a profound impact on the NZF SDCP response, which suggests that NZF SDCP may be useful to get atomic scale information about MOSFET interfaces such as defect identification. We also find that the NZF SDCP amplitude appears to saturate as a function of charge pumping frequency in most cases but not all. We make model calculations to explain this behavior. We also find that the NZF SDCP spectrum broadens with increasing charge pumping frequency, which may be an inherent NZF SDCP phenomenon. We hypothesize that NZF SDCP may also allow for experimental exploration of some magnetoresistance theories regarding interaction times between charge carriers and traps.

Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs* *Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0903203), the National Natural Science Foundation of China (Grant No. 62004033), and China Postdoctoral Science Foundation (Grant No. 2020M683287).

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (ΔV th,sub) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger ΔV th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of ΔV th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious ΔV th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level (E i) and valence band (E v). The maximum ΔV th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states (D it) between E i and E v. These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of ΔV th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.

Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature N₂ Annealing

Effects of high-temperature (1400 °C–1600 °C) N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing on the interface states of 4H- SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the channel mobility of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) were investigated. It is demonstrated that high-temperature N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing is effective not only for the reduction of the interface state density near the conduction band edge but also for that near the valence band edge. N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing improves channel mobility of both n- and p-channel MOSFETs as in the case of nitric oxide (NO) annealing. In particular, the field-effect mobility of the p-channel MOSFETs annealed in an N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient was improved to 17 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, which is 30% higher than that of NO-annealed MOSFETs. The interface state density estimated from the subthreshold slopes in the MOSFETs is much higher than that extracted by the high–low method but is almost comparable to that estimated by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\psi _{\text {s}}$ </tex-math></inline-formula> method in both the cases of interface states near the conduction and the valence band edges. These results suggest that there exist fast states (>1 MHz) near the valence band edge, and these fast states affect the channel mobilities of p-channel SiC MOSFETs as in the case of n-channel MOSFETs.

TEOS-based low-pressure chemical vapor deposition for gate oxides in 4H–SiC MOSFETs using nitric oxide post-deposition annealing

The use of SiO2/4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be problematic due to high interface state density (Dit) and low field-effect mobility (μfe). Here, we present a tetra-ethyl-ortho-silicate (TEOS)-based low-pressure chemical vapor deposition (LPCVD) method for fabricating the gate oxide of 4H–SiC MOSFETs using nitric oxide post-deposition annealing. SiO2/4H–SiC MOS capacitors and MOSFETs were fabricated using conventional wet and TEOS oxides. The measured effective oxide charge density (Qeff) and Dit of the TEOS-based LPCVD SiO2/4H–SiC MOS capacitor with nitridation were 4.27 × 1011 cm−2 and 2.99 × 1011 cm−2eV−1, respectively. We propose that the oxide breakdown field and barrier height were dependent on the effective Qeff. The measured μfe values of the SiO2/4H–SiC MOSFETs with wet and TEOS oxides after nitridation were, respectively, 11.0 and 17.8 cm2/V due to the stable nitrided interface between SiO2 and 4H–SiC. The proposed gate stack is suitable for 4H–SiC power MOSFETs.

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

Physical Study of SiC Power MOSFETs Towards HTRB Stress Based on C-V Characteristics

The quality of the gate-oxide and Oxide/SiC interfaces is one of the crucial issues in the implementation of silicon carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in the industrial power electronic applications. The main goal of this work is to investigate the gate-oxide integrity and to understand the basic phenomena involved on 4H-SiC MOSFET by the mean of Capacitance-Voltage (C-V) characterizations. The paper presents HTRB (High Temperature Reverse Bias) test results on the second and third generations of SiC MOSFETs. The C-V measurements are compared to physical simulation results. The good agreement between 2D numerical simulations and measurements suggests failures related to acceptor interface traps and doping concentration variations.