Abstract
The phenomenon of reduced energy capability of power metal-oxide-semiconductor field-effect transistors (MOSFETs) at high avalanche currents is investigated in commercial 1.2-kV 4H-SiC MOSFETs. Unclamped inductive switching (UIS) measurements as well as electrical transport simulations are used to identify the current paths and maximum avalanche currents, providing insight into the design limits. The investigated devices show a reduced energy capability for avalanche current above 52 A due to the latching of the parasitic bipolar junction transistor (BJT). The BJT also limits the maximum switchable current to ≤102 A. Based on the measurements and simulations, a procedure utilizing UIS measurements for identification of design limits is presented.
Highlights
P OWER metal–oxide–semiconductor field-effect transistors (MOSFETs) undergo avalanche generation when switching in the presence of parasitic inductances [1]
For inductor to peak avalanche currents (IAV) above this value, energy dissipated on the devices under test (DUTs) decreases approximately linearly with current
Results of unclamped inductive switching (UIS) tests show that the devices in this study reached Ecrit for avalanche currents below IAV ≤ 52 for the given test conditions
Summary
P OWER metal–oxide–semiconductor field-effect transistors (MOSFETs) undergo avalanche generation when switching in the presence of parasitic inductances [1]. The secondary mechanism can be due to the limitation of the material, such as reaching intrinsic temperature, or due to a significant leakage through the gate dielectric. It can occur when the parasitic bipolar junction transistor (BJT) latches [2]–[7]. In Si IGBTs, it has been demonstrated that filamentation may occur, where the filament will be pinned to field crowding areas of the parasitic BJTs [8] Research has demonstrated such failures limiting the avalanche current capability in silicon IGBTs using simulations [6], [8] as well as unclamped inductive switching (UIS) measurements [9]. In Si MOSFETs, trench gate [10], [11] and L-shaped structures [12] were investigated and showed a tradeoff between cell design parameter variations and avalanche
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