4H-SiC Metal Oxide Semiconductor Capacitors Research Articles

Simultaneous electric dipoles and flat-band voltage modulation in 4H-SiC MOS capacitors through HfO2/SiO2 interface engineering

We report an approach to simultaneously tune the electric dipoles and flat-band voltage (V FB) of 4H-silicon carbide (SiC) metal-oxide-semiconductor (MOS) capacitors through high-k oxide dielectric interface engineering. With an additional HfO2 thin layer on atomic layer deposition (ALD) of SiO2 film, a dipole layer was formed at the HfO2/SiO2 interface, leading to a small positive shift of the V FB of 0.3 V in 4H-SiC MOS capacitors. The Kelvin probe method was used to examine the dipole layers induced at the direct-contact oxide/4H-SiC interfaces. It was found that a minor difference of 0.3 V in the contact potential difference (V CPD) is observed between the SiO2/4H-SiC and HfO2/SiO2/4H-SiC stacks, which signifies the presence of a weak interface dipole layer at the interface of HfO2 and SiO2. Additionally, investigation of the interface state density reveals that ALD of the HfO2 process had a negligible impact on the quality of the SiO2/4H-SiC interface, suggesting that the observed small positive V FB shift originated from the HfO2/SiO2 interface rather than the SiO2/4H-SiC interface.

Factors Affecting Bias Temperature Instability in 4H-SiC MOS Capacitors

The threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) show instability during normal operation, especially after bias temperature stress (BTS), and this phenomenon is called bias temperature instability (BTI). In this work, to study the factors affecting threshold voltage (Vth) instability of SiC MOSFETs, flat-band voltage (Vfb) instability of 4H-SiC metal-oxide-semiconductor (MOS) capacitors is discussed instead. Some factors, including the polarity of gate bias stress, stress time, and stress temperature, are analyzed by performing one-way bias stress C-V measurements in the devices. Firstly, positive bias stress leads to a positive Vfb shift, and negative bias stress leads to a negative one. Moreover, the Vfb shift appears to exhibit a linear relationship with log (stress time). Furthermore, the Vfb shift decreases over the temperature range of 225 K to 400 K, but slightly increases at 475 K. Finally, the Vfb stability of the MOS devices fabricated by 1200 °C NO post-oxidation annealing (POA) and those fabricated by 1250 °C NO POA is similar.

Detection of near-interface traps in NO annealed 4H-SiC metal oxide semiconductor capacitors combining different electrical characterization methods

Fast near-interface (NI) traps have recently been suggested to be the main cause for poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors. Combining capacitance, conductance, and thermal dielectric relaxation current (TDRC) analysis at low temperatures of nitrided SiC MOS capacitors, we observe two categories of fast and slow near-interface traps at the SiO2/4H-SiC interface. TDRC reveals a suppression of slow near-interface traps after nitridation. Capacitance and conductance analysis reveals a high density of fast NI traps close to the SiC conduction band edge that are enhanced by nitridation. The very fast response of NI traps prevents them from detection using TDRC or deep level transient spectroscopy.

Synergistic passivation effects of nitrogen plasma and oxygen plasma on improving the interface quality and bias temperature instability of 4H-SiC MOS capacitors

Interface properties and bias temperature instability (BTI) determine the performance and stability of SiC metal-oxide semiconductor (MOS) devices. In this work, we propose an electron cyclotron resonance microwave nitrogen–oxygen (NO) mixed plasma post-oxidation annealing (POA) process to improve the interface properties and BTI of 4H-SiC MOS capacitors. Results showed that the NO mixed plasma POA reduces the density of interface traps, maintains the stability of the flat band voltage (Vfb) hysteresis under four successive cycles of positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) at 423 K, and significantly reduces the Vfb hysteresis under alternating PBTS and NBTS at 100 K. The oxide traps remarkably decreased to 2.27 × 1012 cm−2 after NO mixed plasma POA. The related passivation and improvement mechanisms were further studied by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, and density functional theory calculations. The synergistic effects of highly reactive N and O plasma promoted the considerable absorption of N at the interface and prevented further oxidation of the SiC substrate. We also elaborate on the effects of N, O, and NO plasma on the elimination and passivation of O vacancy defects, C-related defects (SiOxCy and C dimer), and Si interstitial defects and discuss implications of the simultaneous suppression of electron and hole trapping.

Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

Bias temperature stresses (BTSs) are critical factors that cause severe threshold voltage (Vth) instability in silicon carbide (SiC) metal-oxide-semiconductor (MOS) devices. In this work, we studied the behavior of flatband voltage (Vfb) instability in 4H-SiC MOS capacitors under various BTSs from low temperature (LT) to high temperature (HT) considering the combined effects of interfacial traps and mobile ions. Results showed that nitrogen and nitrogen–hydrogen plasma passivation improved the Vfb instability. The initial sweeping gate voltage determined the direction of Vfb shift. BTSs from LT to HT induced different capacitance–voltage hysteresis characteristics. The Vfb shift was further separated according to the contribution of the interface trapped, oxide trapped, and mobile ionic charges. At LT, the charge trapping dominated the shift behavior. The interface trap density was also extracted by another high-frequency and quasi-static method, which was the same as the separated interface trap density at 100 K, confirming the separation correctness of Vfb shift. At room temperature, charge trapping and mobile ions with very weak mobility contributed to the Vfb shift. At HT, mobile ions that counteracted the charge-trapping effect determined the Vfb shift, although the additional traps were activated in the interface and oxide. Physical models of Vfb instability under different temperature stresses were proposed. Finally, we chose the 100 K, 273 K, and 423 K to analyze gate bias stresses and stress time induced Vfb instabilities as well as their mechanisms.

Interface properties and bias temperature instability with ternary H–Cl–N mixed plasma post-oxidation annealing in 4H–SiC MOS capacitors

Abstract Interface properties and bias temperature instability (BTI) are the two critical issues that severely restricted the performance and reliability of SiC metal-oxide-semiconductor (MOS) devices. In this work, we simultaneously improved interface properties and BTI in 4H–SiC MOS capacitors by modifying SiC/SiO2 interface via ternary H–Cl–N mixed plasma post-oxidation annealing (POA). Results showed that H–Cl–N mixed plasma POA improved the oxide insulating properties, reduced density of interface traps, and improved the BTI both at low temperature and high temperature. The modification of interface was achieved by enriching H, Cl, and N elements at and near the interface, which not only led to a smoother interface, but also could bond with interfacial traps. The synergistic effects of H, Cl, and N in reducing traps at and near the interface were due to the conversion of the trap levels to or outside the lower half of the SiC bandgap, thereby suppressing electron trapping. Density Functional Theory calculations further indicated that the Cl and N could passivate mobile ions and Si-Si bonds. N passivation and combined N and H passivation were stable and effective in passivating Si-Si bonds and reducing oxygen vacancies.

X-Ray Irradiation on 4H-SiC MOS Capacitors Processed under Different Annealing Conditions

The overall radiation response to X-ray exposure of metal-oxide-semiconductor (MOS) capacitors, subjected to two different post-deposition-annealing (PDA) processes in N2O or POCl3 atmospheres, was investigated by capacitance-voltage (C-V) analyses. The production rate and saturation density of electrically active defects, different for the two oxides, demonstrated an additional contribution to the defects formation coming from the annealing treatements. The higher susceptibility of the POCl3-annealed oxide respect to the N2O annealed is discussed.

Characterization of Reliability in SiC Power Devices

The low intrinsic carrier concentrations, high breakdown voltages, and high thermal conductivities of wide-bandgap semiconductors make them attractive alternatives to traditional Si-based power electronics, especially for high-temperature/power switching applications such as motor drives, hybrid electric vehicles, and photovoltaic inverters. Silicon Carbide (SiC) is an especially strong candidate to replace Si devices due to widespread availability of SiC substrates, vertical device topologies, and the ability to thermally grow a silicon dioxide (SiO2) layer on SiC to serve as a gate dielectric, similar to established Si technology.SiC MOSFETs have been commercially available for over three years with blocking voltage of 1200V and excellent on-state resistances (~80 mΩ). In addition, SiC MOSFETs may be able to operate at higher temperatures than competing Si IGBTs or MOSFETs. Currently the most significant hurdles to market penetration are reliability and cost.SiC MOSFET reliability challenges stem mainly from poor SiC/SiO2 interface quality. When operated under high gate field and temperatures, threshold voltage (VT) instabilities are often observed both in SiC MOSFET [1] and MOS capacitor [2] structures, primarily due to the large number of electrically active SiO2 bulk and SiC/SiO2 interface states [3].The application of a gate voltage (VG) may result in electron (positive VG) or hole (negative VG) injection from the SiC into the oxide, populating traps at the SiO2/SiC interface and/or within the SiO2 bulk. These populated traps alter the surface potential and shift the VT necessary to switch the device. Recent measurements on second-generation commercially available SiC MOSFETs indicate significant progress on this front compared to earlier devices, although appreciable VTshifts still exist for relatively moderate stresses (Fig. 1a).We have characterized 1200 V SiC MOSFETs as well as Junction FETs (JFETs), which do not utilize a gate oxide, at high temperatures under both static and dynamic gate bias stress conditions. SiC JFET devices demonstrate more stable VT than SiC MOSFET devices for both types of gate bias stresses at high temperatures (Fig. 1b). For static gate bias stresses, packaged JFET devices exhibited a negligible VT shift (ΔVT < 2 mV) for temperatures up to 250oC. At higher temperatures, bare JFET die demonstrated ΔVT < 10 mV up to 525oC. Further, in contrast to the SiC MOSFETs, the VTof the SiC JFETs was unaffected by dynamic gate bias stress over the test period, although the sub-threshold leakage current increased with time [4].In addition to monitoring VT shifts, we have calculated the change in density of SiC/SiO2 interface traps (ΔDIT) due to the application of gate stress to MOSFETs. These profiles can be extracted from I-V curves for SiC MOSFETs based on the changes in sub-threshold slope. This technique can either be used to determine ΔDIT (if body doping and gate capacitance are unknown) or absolute DIT at specific energies within the bandgap (if doping and capacitance are known) [5].This work was performed under the DOE Office of Electricity programs managed by Dr. Imre Gyuk. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.[1] A. J. Lelis, et al., "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements," IEEE Trans. Electr. Dev., vol. 55 (8), pp. 1835-1840, 2008.[2] M. J. Marinella, et al., "Evidence of Negative Bias Temperature Instability in 4H-SiC Metal Oxide Semiconductor Capacitors," Appl. Phys. Lett., vol. 90 (25), pp. 253508-253508, 2007.[3] D. K. Schroder, "Progress In SiC Materials/Devices and Their Competition," Int. J. High Speed Electr. and Syst., vol. 21 (1), p. 1250009, Apr 2012.[4] J. Flicker, et al., "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures," High Temperature Electronics Conference (HiTEC), Albuquerque, NM, 2014.[5] D. R. Hughart, et al., "Sensitivity Analysis of a New Technique for Trapped Charge Extraction in SiC MOSFETs from Subthreshold Characteristics " International Reliability Physics Symposium (IRPS), Waikoloa, HI, 2014.

Effects of wet-ROA on shallow interface traps of n-type 4H-SiC MOS capacitors

The effects of wet re-oxidation annealing (wet-ROA) on the shallow interface traps of n-type 4H-SiC metal—oxide—semiconductor (MOS) capacitors were investigated by Gray—Brown method and angle-dependent X-ray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps (Dit) from 0 to 0.2 eV below SiC conduction band edge (EC) of the sample with wet-ROA for the first time, and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species, which results in C release and SiOxCy transformation into higher oxidation states, thus reducing the SiOxCy content and the SiOxCy interface transition region thickness.

Bias-Temperature Instabilities in 4H-SiC Metal–Oxide–Semiconductor Capacitors

Bias-temperature instabilities (BTIs) are investigated for n- and p-substrate 4H-SiC metal–oxide–semiconductor (MOS) capacitors. The midgap voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{ \rm mg})$</tex></formula> shifts positively under positive bias stress at high temperatures for n-substrate capacitors with 67.5-nm nitrided oxides and shifts negatively under negative bias for p-substrate capacitors with 55-nm nitrided oxides. The magnitudes of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm mg}$</tex></formula> shifts are less than 0.5 V for electric fields of magnitudes of approximately <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm$</tex> </formula> 3.1 MV/cm for up to one day of stress at 150 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex> </formula> or 20 min of stress at 300 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex></formula> . Switched-bias stressing at 150 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex></formula> causes partially reversible shifts for the n-substrate capacitors, while the p-substrate capacitors show monotonically increasing negative shifts. Based on the measured temperature dependence of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> $V_{\rm mg}$</tex></formula> shifts, the effective activation energy for BTI that is measured between room temperature and 250 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}\hbox{C}$</tex></formula> is 0.12 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm$</tex></formula> 0.02 eV for the n-substrate capacitors (positive shifts) and 0.23 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm$</tex></formula> 0.02 eV for the p-substrate capacitors (negative shifts). The midgap voltage shifts in these wide-bandgap devices are caused by charge capture at deep interface traps and N-related defects at or near the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{SiC}{-}\hbox{SiO}_{2}$</tex> </formula> interface, which can be enhanced at elevated temperatures by the generation of additional carriers due to the ionization of deep dopants in the SiC during bias-temperature stress.

Sub-bandgap light-induced carrier generation at room temperature in 4H-SiC metal oxide semiconductor capacitors

Carrier generation characteristics in n-type substrate silicon carbide (SiC) metal oxide semiconductor capacitors induced by sub-bandgap energy light are reported. The generation rate is high enough to create an inversion layer in approximately 20 min with monochromatic front side illumination of energy 2.1 eV in 4H-SiC for electric fields less than 1 MV/cm. Generation and recovery results strongly indicate involvement of a metastable defect whose efficiency as a generation center increases under hole-rich and decreases under electron-rich conditions. The generation dependence on bias history and light energy shows the defect to have properties consistent with the metastable silicon vacancy/carbon vacancy-antisite complex (VSi/Vc–CSi).

Reliability Issues of SiC MOSFETs: A Technology for High-Temperature Environments

The wide-bandgap nature of silicon carbide (SiC) makes it an excellent candidate for applications where high temperature is required. The metal-oxide-semiconductor (MOS)-controlled power devices are the most favorable structure; however, it is widely believed that silicon oxide on SiC is physically limited, particularly at high temperatures. Therefore, experimental measurements of long-term reliability of oxide at high temperatures are necessary. In this paper, time-dependent dielectric-breakdown measurements are performed on state-of-the-art 4H-SiC MOS capacitors and double-implanted MOS field-effect transistors (DMOSFET) with stress temperatures between 225°C and 375°C and stress electric fields between 6 and 10 MV/cm. The field-acceleration factor is around 1.5 dec/(MV/cm) for all of the temperatures. The thermal activation energy is found to be ~ 0.9 eV, independent of the electric field. The area dependence of Weibull slope is discussed and shown to be a possible indication that the oxide quality has not reached the intrinsic regime and further oxide-reliability improvements are possible. Since our reliability data contradict the widely accepted belief that silicon oxide on SiC is fundamentally limited by its smaller conduction-band offset compared with Si, a detailed discussion is provided to examine the arguments of the early predictions.

Evidence of negative bias temperature instability in 4H-SiC metal oxide semiconductor capacitors

Generation lifetimes and interface state densities of n-type 4H-SiC metal oxide semiconductor (MOS) capacitors are characterized by using the pulsed MOS capacitor technique. A decrease in lifetime and increase in interface state density occurs when the devices are negatively biased at 400°C. This behavior is consistent with an effect seen in Si∕SiO2 devices known as negative bias temperature instability. A portion of the lifetime degradation caused by this effect can be recovered by removing the negative bias as well as by positively biasing the device.

High-temperature post-oxidation annealing on the low-temperature oxide/4H-SiC(0001)

A silicon–oxide layer was deposited by a low-pressure chemical vapor deposition technique at temperatures as low as 400 °C for gate dielectric material of the 4H-SiC metal–oxide–semiconductor (MOS) capacitors. Interfacial properties such as the amount of effective charge (Neff), interfacial oxide trapped density (Dit) and hot-carrier tolerance of the 4H-SiC(0001) MOS capacitors were evaluated by simultaneous C–V measurement as a dependence of a post-oxidation annealing (POA) at temperatures ranging from 1000 to 1200 °C. It was found that the POA temperature dependence of the Dit was different from that of the Neff. On the other hand, the POA dependence of hot-carrier tolerance was similar to that of the Dit. In consequence, those interfacial properties were sufficiently improved and became stable above the POA temperature of 1100 °C, which corresponds to the softening temperature of SiO2 bulk.