4H-SiC Junction Field Effect Transistor Research Articles

Impact of Dimensions and Doping on the Breakdown Voltage of a Trench 4H-SiC Vertical JFET

In this paper we study the feasibility of the design/fabrication of a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints of the depth of the P+ implantation. The P+ doping profile is obtained using a Monte Carlo implantation simulation. The calculation used a drift-diffusion approach. The JFET aims to achieve a threshold voltage of-3V. We found that this constraint in concomitance with the proposed structure limits the breakdown voltage to approximately 200V. This is the result of a premature breakdown induced by short channel effects, namely Drain Induced Barrier Lowering (DIBL). However, a negative increase in the gate bias represses this short channel effect and improves the breakdown voltage to roughly 1800V. At this gate bias, the breakdown is induced by reaching the critical field strength of 4H-SiC at the gate P+/N junction, which causes avalanche generation of carriers. In addition, we have calculated the dependence of the threshold voltage on the drift doping and pillar width. This work also shows the vulnerability of the design to random fluctuation in the doping profile.

A High-Performance 4H-SiC JFET With Reverse Recovery Capability and Low Switching Loss

A novel high-performance 1700-V 4H-Silicon carbide (SiC) junction field-effect transistor (JFET) with reverse recovery capability and low switching loss is proposed in this article. As for the proposed 4H-SiC JFET, the gate region of the conventional 4H-SiC JFET is split into two segments, one of which is replaced by the source. A Schottky barrier diode (SBD) is integrated in the sidewall of the channel region, which greatly improves the performances of the 4H-SiC JFET. Compared with the conventional 4H-SiC JFET, the numerical simulation results show that the specific ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON},\text{ sp}}$ </tex-math></inline-formula> ), gate–drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text{GD}}$ </tex-math></inline-formula> ), and gate–drain charge ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}_{\text{gd}}$ </tex-math></inline-formula> ) of the proposed 4H-SiC JFET are reduced by 25.57%, 99.96%, and 72.91%, respectively. The switching loss is reduced by about 91%, and the average gate drive power consumption is reduced by more than 36% while the frequency range is from 10 to 400 kHz. The results also demonstrate that the proposed device has good reverse recovery performance and reduces switching loss, compared with the current commercial SiC devices.

Experimental Study on Mitigation of Lifetime-Limiting Dielectric Cracking in Extreme Temperature 4H-SiC JFET Integrated Circuits

While NASA Glenn Research Center’s “Generation 10” 4H-SiC Junction Field Effect Transistor (JFET) integrated circuits (ICs) have uniquely demonstrated 500 °C electrical operation for durations of over a year, this experimental work has also revealed that physical cracking of chip dielectric passivation layers ultimately limits extreme-environment operating lifetime [1-3]. The prevention of such dielectric passivation cracks should therefore improve IC high temperature durability and yield, leading to more beneficial technology adoption into aerospace, automotive, and energy systems. This report describes Generation 10.2, 11.1, and 11.2 die tested under unbiased and unpackaged accelerated age testing at 500 °C, 600 °C, 720 °C, and 800 °C in air-atmosphere ovens for 100-and 200-hour duration. Additional samples were separately subjected to 10 thermal cycles between the same high temperatures (with 10-hour high-temperature soak each cycle) and 50 °C. It is shown that having two stoichiometric Si3N4 layers in the interconnect dielectric stack substantially decreases the amount of dielectric cracking observed following these oven tests.

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460°C, ~9.3 MPa (~92 Earth atmospheres) chemically reactive environment. Here, we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost threefold and were accomplished using prototype SiC JFET chips of more than sevenfold increased complexity. The demonstrated advancement marks a significant step toward realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Prolonged 500°C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.

Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Demonstration of 4H-SiC Digital Integrated Circuits Above 800 °C

Short-term demonstrations of packaged 4H-SiC junction field-effect transistor (JFET) logic integrated circuits (ICs) at temperatures exceeding 800 °C in air are reported, including a 26-transistor 11-stage ring oscillator that functioned at 961 °C ambient temperature believed unprecedented for electrical operation of a semiconductor IC. The expanded temperature range should assist temperature acceleration testing/qualification of such ICs intended for long-term use in applications near 500 °C ambient, and perhaps spawn new applications. Ceramic package assembly leakage currents inhibited the determination of some intrinsic SiC device/circuit performance properties at these extreme temperatures, so it is conceivable that even higher operating temperatures might be obtained from SiC JFET ICs by employing packaging and circuit design intended/optimized for T $\ge800$ °C.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C

Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC’s with two levels of metal interconnect capable of prolonged operation at 500 °C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 °C. A 3-stage oscillator functioned for over 3000 hours at 500 °C in air ambient. Improved reproducibility remains to be accomplished.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.

Prolonged 500 °C Demonstration of 4H-SiC JFET ICs With Two-Level Interconnect

This letter reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 h of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field-effect transistor technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over $\sim 1$ - $\mu \text{m}$ scale vertical topology. Following initial burn-in, important circuit parameters remain stable within 15% for more than 1000 h of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

High temperature characterization of normally-on 4H-SiC junction field-effect transistor

SiC JFETs are considered to be the most promising high-temperature switches. In this paper, the electro-thermal simulation is conducted to investigate the performance and junction temperature of SiC normally-on JFET. The current density will degrade by more than 30% due to the self-heating effect even at room temperature. For a given device, the increase of the gate voltage can help to improve the current density. But the most efficient way to improve the high temperature performance of SiC JFETs is to optimize the structure parameters in design. When the channel width increases from 1.6 μm to 2 μm or the drift-layer width decreases from 14 μm to 7 μm at 300 K, the current handling ability can increase to double or treble even at a small bias. In this case, the junction temperature variation is less than 5 K, which will greatly reduce the device size and improve the reliability.

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

Abstract A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 °C to 500 °C SPICE simulation models of first-order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits

Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 °C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C).

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits prior to deployment in beneficial applications. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuit technology implemented with multilayer interconnects intended for prolonged operation in applications at temperatures up to 773K (500 °C). A 50mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C). We tested each of the following devices: Transmission Line Method (TLM) test structure, discrete JFET with a gate length of 6 µm and width of 12 µm, discrete on-chip capacitor of area about 0.5mm2, 3-stage ring oscillator comprising of 12 JFET transistors and 30 resistors, and one open-circuit trace on the sapphire wafer to test leakage of everything up to the die. These devices resided on a single 3mm x 3mm SiC die that was bonded via die-attach paste to a 50mm sapphire wafer “package” with patterned 1µm thick gold traces. The lateral spacing of gold traces on sapphire was 3.175mm. The die attach paste is conductive, providing backside electrical contact necessary for stable device operation. 25µm diameter gold ball/wedge bonds connected chip pads to gold traces on the sapphire wafer, and 250 µm diameter gold wires with glass fiber insulation connected the sapphire wafer to a terminal strip outside an oven. The die remained uncovered for the duration of the test. The thermal profile started with a ramp at 3K/minute from 300K to 773K. Then the sample remained at 773K for 22 hours. The 22-hour “burn-in” at 773K was performed because significant reductions in leakage have been observed during previous testing at this temperature. The final ramp from 773K to 1150K was at 9K/minute. The JFET and TLM were measured with a digitizing curve tracer, while the capacitor and sapphire wafer leakages were measured with source-measure units. Ring oscillator output was measured with a 10M-Ohm probe AC-coupled to digitizing oscilloscope. The devices were continuously biased, but only measured every 90 seconds during the thermal ramps and every 2 hours during the 773K “burn in.” The 3-stage ring oscillator frequency decreased from ~850 kHz at 773K to ~660 kHz at 1000K with output amplitude that decreased from 130mV to 20 mV. The JFET exhibited saturation current of 280 µA at 300K that decreased to 50 µA at 1000K. The n-type TLM exhibited specific contact resistance of less than 4 x 10-4 µÙ cm2 throughout the test, and a sheet resistance of 5 kµÙ/square at 300K that increased to 38 kµÙ/square at 1000K with approximately T2power law behavior. No leakage above open-circuit noise floor was observed from the capacitor at 20V bias until 600K. The leakage increased with temperature until 686K at 378 µA at which point the 20V leakage began to drop even while the temperature was increasing. By the time the capacitor had reached the start of the 773K burn in period the leakage had dropped to ~100 µA. The capacitor had measurable leakage again when heated to above 990K and then the max leakage remained below 100 µA. The sapphire did not have measurable 20V leakage until 850K, which increased to 68 nA at 1000K. Above 1000K all devices started to demonstrate behavior consistent with loss of the backside bias connection. Upon cooling and inspection it was found that the backside contact metal on the die and the gold trace area on the sapphire became transparent where there was die attach paste. There were cracks in the on-chip SiO2dielectric formed from low pressure chemical deposition (LPCVD) using tetraethyl orthosilicate (TEOS) precursor at the corners of some metal traces. Some of the gold ball bonds wires had melted. The peak oven temperature reached 1150K before the oven was turned off so a clear sequence of causality is hard to determine; therefore, electrical data reported is only to 1000K corresponding to apparent loss of backside bias.

Low Earth Orbit Space Environment Testing of Extreme Temperature 6H-SiC JFETs on the International Space Station

This paper reports long-term electrical results from two 6H-SiC junction field effect transistors (JFETs) presently being tested in Low Earth Orbit (LEO) space environment on the outside of the International Space Station (ISS). The JFETs have demonstrated excellent functionality and stability through 4600 hours of LEO space deployment. Observed changes in measured device characteristics tracked changes in measured temperature, consistent with well-known JFET temperature-dependent device physics.

Prolonged 500 °C Operation of 6H-SiC JFET Integrated Circuitry

This paper updates the long-term 500 °C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 °C with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 °C before failure.

Fabrication and Testing of 6H-SiC JFETs for Prolonged 500 °C Operation in Air Ambient

This paper reports on the fabrication and testing of 6H-SiC junction field effect transistors (JFETs) and a simple differential amplifier integrated circuit that have demonstrated 2000 hours of electrical operation at 500 °C without degradation. The high-temperature ohmic contacts, dielectric passivation, and packaging technology that enabled such 500 °C durability are briefly described. Key JFET parameters of threshold voltage, on-state resistance, transconductance, and on-state current, as well as the gain of the differential amplifier integrated circuit, exhibited less than 7% change over the first 2000 hours of 500 °C operational testing.