Inverter Leg Research Articles

A PI-type dead-time compensation method for vector-controlled GTO inverters

In the case of voltage-source gate-turn-off thyristor (GTO) inverters, the conventional dead-time compensation methods do not work well, since the terminal voltage of an inverter leg is not constant during the dead-time period, due to the presence of the snubber circuit. We propose a closed-loop dead-time compensation method that regulates the voltage error by a proportional-integral (PI)-type compensator. We show its superior performance by the reduction in current ripple and in the sixth harmonic component of the motor current in the synchronous frame.

4000V-300A Eight-Level IGBT Inverter Leg

The application field of the 1200 V IGBT devices is usually limited to a dc-link voltage up to about 600 V. In order to extend this field, new structures have been developed. In this paper, an inverter leg made of seven nested cells is presented (Fig. 7), With this structure, it is possible to increase the d.c.-link voltage of IGBT inverter up to 4000 Vdc and provide a 300 Arms current. Moreover, the output waveforms fully benefit from the increased number of switches (Fig. 4).

Modeling of multilevel converters

In this paper, the imbricated cells multilevel converters are studied and modeled from a control viewpoint. These converters make use of several switches connected in a series, which allows using switches with reduced voltage ratings; these low voltage switches have lower conduction losses and can switch at higher frequency. In addition to this feature common to all converters using series connected switches, the control signals of multilevel converters can be phase shifted to increase the apparent switching frequency and improve the dynamic performances of the whole converter. It is shown that a multilevel inverter leg, composed of p pairs of switches and p-1 capacitors, forms a multivariable nonlinear system that cannot be properly modeled by standard methods such as state-space averaging. The transient behavior of this system depends on the current harmonics and their phase shift with the different control signals. A specific model is detailed, studied, and used to illustrate the properties of these converters. In particular, the natural balancing of the voltage across the switches is demonstrated and the time constants involved in this process are determined.

Power losses in PWM-VSI inverter using NPT or PT IGBT devices

This paper investigates the power losses for two different IGBT technologies (nonpunch through and punch through) for use in PWM-VSI inverters in order to choose the right device technology for a given application. A loss model of the inverter is developed based on experimental determination of the power losses. The loss model is used on two different modulation strategies which are a sine wave with a third harmonic added and a 60/spl deg/-PWM modulation where only two inverter legs are active at the same time. The two IGBT technologies are characterized on an advanced measurement system which is described. The total power losses in the inverter are estimated by simulation at different conditions and it is concluded that the nonpunch through (NPT) technology is most useful for higher switching frequencies, while the punch through (PT) technology is especially useful at lower switching frequencies and high load currents. It is also concluded that the 60/spl deg/-PWM modulation has the lowest power losses and the power losses are almost independent of phase angle cos(/spl phi/) for normal motor operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Imbricated Cells Multi-Level Voltage-Source Inverters for High Voltage Applications

SummaryIn the field of High Voltage Power Conversion, various techniques have been developped to use series-connected switches.Plain series connection of switches is the first solution and its drawbacks are now well-known (static and dynamic voltage sharing difficulties that require selecting paired switches or using sophisticated control techniques, high dV/dts generated by the synchronous commutation of all the switches, output waveform that does not benefit from the increased number of switches...).The “neutral point clamped” technique introduced in the early 80s improves voltage sharing and dV/dts, and gives a three-level output waveform.More recently a new multilevel topology has been introduced; compared to former techniques, it really solves the problem of voltage sharing and dV/dts, and gives a three-level output waveform with cancellation of the harmonic at the switching frequency.In this paper, it is shown that this technique can be easily generalized to voltage-source inverter legs with any num...

Compensating for dead time degradation of PWM inverter waveforms

The output voltage waveforms of a bridge inverter using some form of modulation strategy, such as pulse width modulation (PWM), are not the same as the ideal modulated waveforms because of the effect of ‘dead time’. This is the short period of time that is allowed to elapse for safety reasons between switching one device in an inverter leg off and the other device on. It has been found that the dead time causes a reduction in the fundamental component of the output voltage and introduces low order harmonics which are not intrinsically present in the ideal modulated waveforms.In variable speed drive systems the reduction in fundamental voltage causes a reduction in the torque. Furthermore, with synchronous modulation strategies there is a step change in torque when a ‘gear change’ takes place. In uninterruptible power supply (UPS) systems the low order harmonics are difficult to remove, with the result that the fundamental output voltage is contaminated.Methods of compensating for dead time are proposed and investigated and it is shown that its effects can be substantially eliminated. Tests with a compensated variable speed drive, using an inverter fed induction motor, demonstrate that the torque perturbations at a gear change are now negligible. Similarly, in a UPS application the low order harmonics are found to be removed from the filtered output voltage when dead time compensation is introduced.

A split-wound induction motor design to improve the reliability of PWM inverter drives

Stator windings have been designed for the three-phase induction motor to protect the PWM inverter bridge against simultaneous-conduction fault currents. Rather than adding inductance in each inverter leg to control fault currents, the design lets the primary leakage inductance of the motor stator windings perform the fault current control function. Appropriate separation of the windings in the stator slots increases the protection afforded. A 4 kW, two-pole, squirrel-cage induction motor, together with a 5 kW MOSFET inverter drive switching at 20 kHz, illustrates that excellent motor performance is possible with the new winding configurations. The motor power rating and torque/slip curves obtained at various speed settings with the new drive are close to those of a motor using standard stator windings. The protection afforded by the windings is shown to increase with the motor power and voltage rating.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient Snubbers for Voltage-Source GTO Inverters

The two gate turn-off thyristors in the phase leg of a voltage-source inverter are provided with a series center-tapped inductance snubber and shunt capacitor snubbers having a single discharge resistor and only two auxiliary diodes. This arrangement minimizes the number of components and allows reduction of capacitor size, thereby reducing the snubber losses. The resistor may be replaced by a transformer which conserves a substantial part of the energy trapped in both the series and shunt snubbers.

Harmonic distortion in PWM inverter output waveforms

It is usual to provide a short “dead time” between switching one device in an inverter leg off and switching the other device on, to prevent them conducting simultaneously. It is known that this expedient modifies the harmonic content of the output voltage waveform of a pulse-width modulation (PWM) inverter. It changes the amplitude of the fundamental component, which can be significant in variable-speed drives when the frequency ratio is changed. It also introduces low-amplitude, low-order harmonic components which are not wanted in uninterruptible power supplies when voltage waveforms of high purity are demanded. This problem has been treated quantitatively and it has been shown by a systematic set of experiments that the proposed theoretical method is reliable. It has been found that the amplitudes of the odd harmonics produced depend only upon the ratio of the dead time to the period of the switching frequency. Similarly the amplitudes of the even harmonics, which only occur with even frequency ratios, depend on the ratio of the dead time to the period of the fundamental frequency. Accordingly it has been possible to present generalised curves which allow the design engineer to estimate the amplitudes of these harmonics for any combinations of fundamental and modulating frequencies. These results have been presented in such a way that they are applicable to both single-phase and 3-phase PWM inverters.

Protection methods for power-transistor circuits

The paper proposes a number of protection methods which can be used with power transistors in power-control units. They give satisfactory protection against simultaneous conduction of the two devices in an inverter leg. The techniques, which are independent of the control electronics and base-drive circuits, are simple and reliable to implement. They include an instantaneous and electrically isolated method of fault indication, a fast-acting crowbar circuit and a means of diverting the current away from the power devices in the event of a fault.