4-input Lookup Tables Research Articles

Parallelized Radix-4 Scalable Montgomery Multipliers

This paper describes a parallelized radix-4 scalable Montgomery multiplier implementation. The design does not require hardware multipliers, and uses parallelized multiplication to shorten the critical path. By left-shifting the sources rather than right-shifting the result, the latency between processing elements is shortened from two cycles to nearly one. Multiplexers are used to select precomputed products. Carry-save adders propagate carry bits before words are discarded. The new design can perform 1024-bit modular exponentiation in 9.4 ms and 256-bit exponentiation in 0.38 ms using 4997 Virtex2 4-input lookup tables, while consuming 30% fewer LUTs than a previous parallelized radix-4 design. This is comparable to radix-2 for long multiplies and nearly twice as fast for short ones.

A Dynamical Machine Control System using Simple Processing Unit Based-on FPGA

This paper aims to design a dynamic machine control system device. The proposed dynamic device models are a combination architecture of memory and Arithmetic-Logic Unit (ALU). The configuration of the memory has used a random access memory (RAM), and the configuration of ALU is the core of the central processing unit (CPU), which consists of two functions, namely the arithmetic unit and the logical unit. In this paper, the arithmetic unit consists of addition, subtraction, multiplication, and division, whereas the logical units are AND, OR, NOT, and XOR. The shifter circuit in this paper was also applied to complete the programming code instructions in a software approach. The arithmetic unit and logic unit selector path in the ALU configuration employed a multiplexer circuit. This paper used a top-down design technique by determining the components in implementation. By knowing the function and work of these components, it is much easier to combine the components employing the configuration code of the hardware description language, namely a Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The implementation of the VHDL code was configured into the Xilinx Spartan-3E Field Programmable Gate Array (FPGA) to determine the component consumption and the resulted delay time. The results obtained from the configuration of the ALU components consume 26 slices, 50 4-input look-up table (LUT), 17 input/output (I/O), and 17 Bonded IO, while the component delay time is 11,413 ns.

An Improved Area Efficient 16-QAM Transceiver Design using Vedic Multiplier for Wireless Applications

In this research article, an improved area efficient 16-Quadrature Amplitude Modulation (QAM) transceiver design is introduced using Vedic multiplier. The 16-QAM design is transmitted using Pseudo Random Binary Sequence (PRBS) and modulated by changeable clock frequencies. The Vedic multiplier uses Urdhva Tiryakbhyam (Vertical and Crosswise) method of multiplication to reduce the undesirable steps and generates parallel partial products. Compressor adders are used in the Vedic multipliers, which helps to increase the speed of multiplication process and reduces the carry delay. Four Compressor adders namely 5-3, 10-4, 15-4 and 20-5 are used in a 16-bit Urdhva Tiryakbhyam Vedic multiplier to add its partial products. The proposed 16-QAM design is implemented using Spartan-3 XC3S200-5 pq208 Field Programmable Gate Array (FPGA) device which occupies 672 slices, 1102 4-input Look up Tables (LUTs) and 39 mW of power consumption. The Vedic multiplier based 16-QAM transceiver design reduces 17.2% slices and 4.5% 4-input LUTs. The 16-QAM is a preferred digital modulation method in the Orthogonal Frequency Division Multiplexing (OFDM) system, which reduces bit errors and noise effects during data transmission. The OFDM transceiver design is used in the high-speed wireless communication by excellence of its Multi-carrier modulation method.

Efficient Utilization of FPGA Using LUT-6 Architecture

Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions (Mux8, Mux16, Mux32, Mux64, SOP64, OR40 and AND40).we show our results in terms of LUTs and Slices and these results are much better as compare to previously reported results that based on 4-input LUTs.

A radiation-hardened SOI-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 × 1011 rad(Si)/s and a neutron fluence immunity of 1 × 1014 n/cm2.

Reconfigurable Blocks Based on Balanced Ternary

Silicon-on-Insulator CMOS fabrication technologies are now available that offer a number of unique advantages including the availability of multiple simultaneous transistor thresholds. This paper proposes and analyzes a number of circuits for a reconfigurable array organization based on a balanced ternary logic system in which the logic set {??1, 0,?+?1} maps directly to equivalent voltage levels {?1V, 0V, +1V}. A number of low-power, high-speed components, such as a ternary buffer, flip-flop and look-up table, are described and simulated based on the characteristics of a commercially available silicon-on-sapphire process. A brief analysis indicates that the circuits will be capable of operating at the 22 nm technology node and beyond. A simple example of a Sigma-Delta Modulated FIR filter is mapped to the array and some preliminary estimates are made of its performance and area based on both 3-input and 4-input look-up tables. The simulated ternary array is shown to be capable of operating at clock speeds of more than 200 MHz such that it will readily support standard video bandwidths at useful over-sampling ratios.

Post-Placement Interconnect Entropy

We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device (PLD) [or field-programmable gate array (FPGA)] and a useful measure of its routing flexibility. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.

ROM to DSP block transfer for resource constrained synthesis

Modern field programmable gate array (FPGA) architectures are moving towards heterogeneity with the increasing inclusion of coarse grained elements such as embedded multipliers and RAMs. This has given rise to a multi-dimensioned resource-based measure of design area, very different from the traditional application-specific integrated circuit figure of silicon area. In order for a designer to use these heterogenous elements in their design, they must usually specifically instantiate them. Heterogeneous elements not used in a design remain unused on the device, consuming leakage power, silicon area and manufacturing costs. Method of transferring functionality normally implemented in embedded ROMs and 4-input look-up tables (4-LUTs) onto unused digital signal processor (DSP) blocks is proposed. The paper proceeds to include this method in a synthesis system incorporating the idea of resource constrained synthesis, where a design is mapped to an FPGA considering user and device constraints on heterogenous element usage, based on an extension to the Altera Quartus II synthesis software. Results have been obtained, showing an improvement over existing methods in 76% of the 21 ROMs examined. Further results have been obtained from applying this approach with the synthesis system to benchmark algorithms. In the designs examined, the number of possible implementations has increased by two to four times over Altera Quartus.

Efficient fpga-implementation of two's complement digit-serial/parallel multipliers

This paper presents an efficient implementation of digit-serial/parallel multipliers on 4-input look-up table (LUT)-based field programmable gate arrays (FPGAs). This subset of FPGA devices hide individual gate delays and add important wiring delay. These two facts produce important changes over the theoretical advantages of each topology. Architectural transformations are applied to obtain topologies with minimum logic depth and where the maximum clock speed is limited by the FPGA technology. The main results of applying those transformations to the different multipliers have been quantified for Altera FLEX10K family, and the conclusions have been extrapolated to other FPGA families.