3D NoC Research Articles

TEFLON: Thermally Efficient Dataflow-aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures

Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architectures are used extensively to accelerate inferencing/training with convolutional neural networks (CNNs). Three-dimensional (3D) integration is an enabling technology to integrate many PIM cores on a single chip. In this work, we propose the design of a t hermally e fficient data flo w-aware monolithic 3D (M3D) N oC architecture referred to as TEFLON to accelerate CNN inferencing without creating any thermal bottlenecks. TEFLON reduces the Energy-Delay-Product (EDP) by 42%, 46%, and 45% on an average compared to a conventional 3D mesh NoC for systems with 36-, 64-, and 100-PIM cores, respectively. TEFLON reduces the peak chip temperature by 25 K and improves the inference accuracy by up to 11% compared to sole performance-optimized SFC-based counterpart for inferencing with diverse deep CNN models using CIFAR-10/100 datasets on a 3D system with 100-PIM cores.

A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks

This comprehensive review explores the advancements in processing-in-memory (PIM) techniques and chiplet-based architectures for deep neural networks (DNNs). It addresses the challenges of monolithic chip architectures and highlights the benefits of chiplet-based designs in terms of scalability and flexibility. This review emphasizes dataflow-awareness, communication optimization, and thermal considerations in PIM-enabled manycore architectures. It discusses tailored dataflow requirements for different machine learning workloads and presents a heterogeneous PIM system for energy-efficient neural network training. Additionally, it explores thermally efficient dataflow-aware monolithic 3D (M3D) NoC architectures for accelerating CNN inferencing. Overall, this review provides valuable insights into the development and evaluation of chiplet and PIM architectures, emphasizing improved performance, energy efficiency, and inference accuracy in deep learning applications.

A 3D Hybrid Optical-Electrical NoC Using Novel Mapping Strategy Based DCNN Dataflow Acceleration

A 3D Hybrid Optical-Electrical NoC Using Novel Mapping Strategy Based DCNN Dataflow Acceleration

RLARA: A TSV-Aware Reinforcement Learning Assisted Fault-Tolerant Routing Algorithm for 3D Network-on-Chip

A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with good scalability, a small area, and high performance using vertical through-silicon vias (TSV). However, the failure rate of TSV, which is higher than that of horizontal links, causes unpredictable topology variations and requires adaptive routing algorithms to select the available paths dynamically. Most works have aimed at the congestion control for TSV partially 3D NoCs to bypass the TSV reliability issue, while others have focused on the fault tolerance in TSV fully connected 3D NoCs and ignored the performance degradation. In order to adequately improve reliability and performance in TSV fully connected 3D NoC architectures, we propose a TSV-aware Reinforcement Learning Assisted Routing Algorithm (RLARA) for fault-tolerant 3D NoCs. The proposed method can take advantage of both the high throughput of fully connected TSVs and the cost-effective fault tolerance of partially connected TSVs using periodically updated TSV-aware Q table of reinforcement learning. RLARA makes the distributed routing decision with the lowest TSV utilization to avoid the overheating of the TSVs and mitigate the reliability problem. Furthermore, the K-means clustering algorithm is further adopted to compress the routing table of RLARA by exploiting the routing information similarity. To alleviate the inherent deadlock issue of adaptive routing algorithms, the link Q-value from reinforcement learning is combined with the router status based in buffer utilization to predict the congestion and enable RLARA to perform best even under a high traffic load. The experimental results of the ablation study on simulator Garnet 2.0 verify the effectiveness of our proposed RLARA under different fault models, which can perform better than the latest 3D NoC routing algorithms, with up to a 9.04% lower average delay and 8.58% higher successful delivered rate.

An efficient adaptive routing algorithm for the Co-optimization of fault tolerance and congestion awareness based on 3D NoC

In this paper, we propose an adaptive, fault-tolerant, and congestion-aware (AFTC) routing algorithm. It improves the overall network performance of three-dimensional Network-on-Chip (3D NoC) in terms of deadlock-free, adaptability, fault tolerance, and balanced traffic. Firstly, the algorithm proposed 12 turn models to avoid deadlock problems. Then, the adaptability of the algorithm is improved by using the three-dimensional diagonal region division method. At the same time, the AFTC can reduce the number of turn-around steps during fault tolerance. Finally, the AFTC can balance traffic by setting different congestion thresholds. Compared with Vertical-Mesh-Conscious-Dynamic (VMCD) algorithm in terms of average packet delay and throughput, the AFTC algorithm can improve the throughput by an average of 27.29 % and 18.62 % while reducing the average delay time in different fault rates under uniform traffic and hotspot traffic patterns, respectively.

AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip

Unlike conventional 2D Networks-on-Chip (NoCs), 3D NoCs offer a scalable and energy efficient on-chip communication. Vertical die stacking of 3D NoCs is enabled using inter-layer Through-Silicon Via (TSV) links. However, TSV technology suffers from low reliability and high fabrication costs. To mitigate these costs, Partially Connected 3D NoCs (PC-3DNoCs), which use fewer vertical TSV links, have been introduced. However, with fewer vertical links (a.k.a. elevators), elevator-less routers will have to send their traffic to nearby elevators for inter-layer traffic, increasing the traffic load and congestion at these elevators and potentially reducing performance. Therefore, it is important that elevator-less routers choose elevators that balance the traffic load among the available elevators. To address this problem, this paper presents an <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ad</u> aptive congestion- and energy-aware <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ele</u> vator-selection algorithm, called AdEle+. AdEle+ employs an offline multi-objective simulated-annealing-based optimization to find good elevator subsets for routers. In addition, during high traffic loads, AdEle+ uses an adaptive and online elevator selection algorithm to select an elevator from the elevator subset to dynamically manage traffic congestion on elevators. Moreover, in low congestion circumstances, AdEle+ switches to a minimal distance selection to improve energy efficiency. Compared to state-of-the-art selection algorithms under various PC-3DNoC configurations and traffic patterns, AdEle+ reduces the average latency by 9.5% on average and up to 11.2% while reducing the hardware overhead by 10.1% due to its efficient online selection in the routers.

SpecMap: An efficient spectral partitioning based static application mapping algorithm for 2D mesh NoCs

SummaryNetwork‐on‐chip (NoC) is adopted as a flexible and effective communication backbone by multiprocessor systems with core counts ranging from a few to hundreds. The performance of NoC based systems greatly rely on the communication between cores when two dependent tasks of an application are mapped to these cores. Hence, application mapping becomes a critical issue in NoC‐based systems as it affects the overall performance of the system. Application mapping aims to reduce the communication among the cores by carefully mapping the highly communicating tasks. Most of the existing static mapping approaches consider only single‐task platforms. In this article, we propose an efficient multi‐task static mapping algorithm called , for regular 2D NoC systems. consists of three stages namely, (i) graph partitioning, (ii) topology clustering, and (iii) mapping. In the graph partitioning stage, accurately identifies and groups the highly communicating tasks based on spectral graph partitioning. Then, the clustering and mapping stages allocate the most communicating tasks in the same or adjacent multi‐tasking cores. It also eliminates the interference between multiple applications by mapping them into different clusters of the NoC network. Simulations of have been conducted on different synthetic and real‐life applications using Gem5 simulator. The simulation results show considerable improvements for SpecMap in terms of communication cost, average network latency, energy consumption, throughput, and execution time as compared to the state‐of‐the‐art algorithms.

Analysis of 3D NoC Router Chip on Different FPGA for Minimum Hardware and Fast Switching

Analysis of 3D NoC Router Chip on Different FPGA for Minimum Hardware and Fast Switching

Multiobjective piecewise regressive elitism spotted hyena optimized mapping for 3D NoC architecture design

Multiobjective piecewise regressive elitism spotted hyena optimized mapping for 3D NoC architecture design

Approximate Priority Hybrid 3DNoC Buffered-Bufferless Router

This paper introduces a novel 3D NoC router that combines buffered and bufferless routing with approximate priority comparison when deflecting flits. Our proposal is a modification of an asymmetrical router that is buffered in the z dimension ports and bufferless in the x and y dimension ports. Flits that request output ports in the x and y dimensions are granted or deflected based on approximate, instead of accurate, priority comparison. Experimental results show that the proposed router, in addition to effectively combining the advantages of both buffered and bufferless routers, achieves additional performance and area gains due to the reduced logic required for approximate priority comparison in flit deflections. Experimental results using synthetic and realistic traffic show that the proposed router begins to saturate at a significantly higher injection rate than a bufferless router, but at a slightly lower injection rate than when using accurate priority comparison. Furthermore, the proposed router achieves higher clock frequencies and a reduced area compared to bufferles routers due to the simpler permutation network. The increased routing efficiency is shown to also translate to energy gains.

TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip.

The die-stacking structure of 3D network-on-chips (3D NoC) leads to high power density and unequal thermal conductance between different layers, which results in low reliability and performance degradation of 3D NoCs. Congestion-aware adaptive routing, which is capable of balancing the network's traffic load, can alleviate congestion and thermal problems so as to improve the performance of the network. In this study, we propose a traffic- and thermal-aware Q-routing algorithm (TTQR) based on Q-learning, a reinforcement learning method. The proposed algorithm saves the local traffic status and the global temperature information to the Q1-table and Q2-table, respectively. The values of two tables are updated by the packet header and saved in a small size, which saves the hardware overhead. Based on the ratio of the Q1-value to the Q2-value corresponding to each direction, the packet's output port is selected. As a result, packets are transferred to the chosen path to alleviate thermal problems and achieve more balanced inter-layer traffic. Through the Access Noxim simulation platform, we compare the proposed routing algorithm with the TAAR routing algorithm. According to experimental results using synthetic traffic patterns, our proposed methods outperform the TAAR routing algorithm by an average of 63.6% and 41.4% in average latency and throughput, respectively.

Thermal-aware routing algorithm in partially connected 3D NoC with dynamic availability for elevators

Thermal-aware routing algorithm in partially connected 3D NoC with dynamic availability for elevators

Thermal-aware directional and adaptive routing algorithm for 3D network-on-chip

Due to the tier architecture &lt;span lang="EN-US"&gt;of 3D network-on-chip (3D-NoC), reducing the thermal hotspot within the chip is challenging as a cooling mechanism that lies merely on the single side of a chip. High power density in 3D NoC is responsible for reliability degradation and thermal difficulties. Thermal-aware routing becomes substantial to handle thermal difficulties and diffusion of heat to the cooler regions. Thermal-aware routing focuses on bypassing hotspot areas by selecting cooler areas. Existing thermal-aware routing algorithms adopt slightly cooler but longer and extended paths, due to lack of ability to know the proximity of the destination's location, which aggravate thermal issues. This work presents a novel thermal-aware directional and adaptive routing algorithm. Objective of the proposed algorithm is to strive to find the best possible neighbour to reach closer to the proximity of the destination. The proposed algorithm can adaptively choose any suitable neighbour that can lead packets closer to the destination at each intermediate node. The performance of the proposed algorithm is evaluated and compared with existing thermal-aware routing algorithm in a simulator environment. Simulation results demonstrate that the proposed method outperformed its counterpart in terms of average delay with 11-26% improvement, total hop counts with 8-24% reduction under various traffic conditions and improvement in overall thermal profiling of the chip.&lt;/span&gt;

Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design

Purpose. Networks-on-Chip (NoC) is a network-based communication between operating cores and intellectual property (IP) cores integrated on the same chip. An efficient design of NoC ensures high-speed data transfer and minimum essential connections in large-scale multicore, low power applications. Design/methodology/approach. A unique technique called Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory (MDRABOMWDGT) is introduced for an efficient Network-on-Chip architecture design. The main aim of the proposed technique is to find efficient operating cores integrated on the chip with minimum time. Initially, a set of IP cores are listed with their connections from the benchmark dataset. Then Multicriteria Deming Regressive African Buffalo Optimization is applied to the topology for mapping strategy on 3D NoC, with communication metrics such as throughput, latency, and computation time. The optimization technique initializes the population of cores in search space. For each core in the network, communication metrics are measured; then Deming regression is applied to analyze multicriteria functions for minimizing computation time. Further, fitness is measured to get an optimal IP core for improving the performance of mapping in 3D NoC. Findings. Comprehensive experimental evaluation is conducted using a benchmark dataset, communication metrics are measured, and results show significant improvement in performance with respect to energy parameters compared to state-of-the-art works. Originality/value. The mapping strategy for 3D NOC is developed and the results are compared with the state-of-the-art techniques.

LETHOR: a thermal-aware proactive routing algorithm for 3D NoCs with less entrance to hot regions

LETHOR: a thermal-aware proactive routing algorithm for 3D NoCs with less entrance to hot regions

STTAR: A Traffic- and Thermal-Aware Adaptive Routing for 3D Network-on-Chip Systems

Since the three-dimensional Network on Chip (3D NoC) uses through-silicon via technology to connect the chips, each silicon layer is conducted through heterogeneous thermal, and 3D NoC system suffers from thermal problems. To alleviate the seriousness of the thermal problem, the distribution of data packets usually relies on traffic information or historical temperature information. However, thermal problems in 3D NoC cannot be solved only based on traffic or temperature information. Therefore, we propose a Score-Based Traffic- and Thermal-Aware Adaptive Routing (STTAR) that applies traffic load and temperature information to routing. First, the STTAR dynamically adjusts the input and output buffer lengths of each router with traffic load information to limit routing resources in overheated areas and control the rate of temperature rise. Second, STTAR adopts a scoring strategy based on temperature and the number of free slots in the buffer to avoid data packets being transmitted to high-temperature areas and congested areas and to improve the rationality of selecting routing output nodes. In our experiments, the proposed scoring Score-Based Traffic- and Thermal-Aware Adaptive Routing (STTAR) scheme can increase the throughput by about 14.98% to 47.90% and reduce the delay by about 10.80% to 35.36% compared with the previous works.

Pareto Technique Optimization for 3d Noc Architecture

Pareto Technique Optimization for 3d Noc Architecture

Energy efficient 3D network-on-chip based on approximate communication

Technology advancement and integration of many cores into a chip lead to high-performance parallel architectures in computing systems. Three-dimensional Network-on-Chips (3D NoCs) have been adopted as a promising architecture in the communication of many-core systems and present lower latency and area compared to 2D NoCs, and they introduce the higher performance. However, 3D NoCs possess thermal challenges due to the high power consumption of 3D routers. The approximation can be used in communication in NoCs to reduce the congestion and latency in the network in error-tolerant applications. In this paper, we employ an approximation mechanism to truncate data packets based on the approximate nature of their applications. So, we reduce network congestion, data volume on communication, and latency. This approach makes it possible to use energy-saving methods in an efficient way, as the network congestion and resource workload are decreased. To show the approach, after employing approximation in communication, we modify the architecture of the routers and links by applying the voltage scaling technique, which is controlled based on the network congestion and approximate regions of the applications. Therefore, the amount of energy saving due to employing the voltage scaling is significantly increased, which alleviates the thermal problems in 3D NoCs. Simulation results indicate that our approach reduces the energy consumption by 21.6% while reducing the latency by 22% compared to some related works for NoCs, with only about 1.3% hardware overhead.

Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs

We introduce Ratatoskr , an open-source framework for in-depth power, performance, and area (PPA) analysis in Networks-on-Chips (NoCs) for 3D-integrated and heterogeneous System-on-Chips (SoCs). It covers all layers of abstraction by providing an NoC hardware implementation on Register Transfer Level (RTL), an NoC simulator on cycle-accurate level and an application model on transaction level. By this comprehensive approach, Ratatoskr can provide the following specific PPA analyses: Dynamic power of links can be measured within 2.4% accuracy of bit-level simulations while maintaining cycle-accurate simulation speed. Router power is determined from RTL-to-gate-level synthesis combined with cycle-accurate simulations. The performance of the whole NoC can be measured both via cycle-accurate and RTL simulations. The performance (i.e., timing) of individual routers and the NoC area are obtained from RTL synthesis results. Despite these manifold features, Ratatoskr offers easy two-step user interaction: (1) A single point-of-entry allows setting design parameters. (2) PPA reports are generated automatically. For both the input and the output, different levels of abstraction can be chosen for high-level rapid network analysis or low-level improvement of architectural details. The synthesizable NoC-RTL model shows improved total router power and area in comparison to a conventional standard router. As a forward-thinking and unique feature not found in other NoC PPA-measurement tools, Ratatoskr supports heterogeneous 3D integration that is one of the most promising integration paradigms for upcoming SoCs. Thereby, Ratatoskr lays the groundwork to design their communication architectures. The framework is publicly available at https://github.com/ratatoskr-project .

FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC

FT-PDC: an enhanced hybrid congestion-aware fault-tolerant routing technique based on path diversity for 3D NoC