3D NAND Structure Research Articles

Hafnia-Based Ferroelectric Transistor with Poly-Si Gates for Gate-First Three-Dimensional NAND Structures.

Ferroelectric transistors based on hafnia-based ferroelectrics have emerged as promising candidates for next-generation memory devices. Additionally, hafnia-based ferroelectric transistors are suggested for three-dimensional (3D) memory devices, such as 3D ferroelectric NAND. This paper investigates the utilization of poly-Si as a gate material for hafnia-based ferroelectric transistors in 3D NAND structures. Conventional gate materials, such as TiN or W, are usually deposited in 3D NAND structures by using the gate-last process, which requires an additional gate replacement process. We demonstrate that poly-Si can be used as a gate material for hafnia-based ferroelectric transistors. We show that the 3D ferroelectric NAND based on the poly-Si gate can be fabricated by a simpler gate-first process without requiring a gate replacement process. Our findings underscore the potential of poly-Si as a gate material for ferroelectric transistors and 3D ferroelectric NAND.

Investigation of thermal stress effects during annealing of hafnia-made thin film using molecular dynamics simulations

Hafnia or hafnium oxide is a high-κ dielectric material with paramount importance in the realm of semiconductor devices. Recent advancements in 3D device structures require a few nanometer-thick conformal films on non-planar substrates. During the fabrication stage, the annealing process of thin films has been discovered to mitigate delamination issues at the film-substrate interface. However, it has been observed that the residual stress, which emerges as the film cools to room temperature, may lead to delamination. In this study, we propose an idealized atomistic model to mimic the critical region of a 3D-NAND structure, to get insights into the effect of thermal stress and delamination during the annealing of hafnia-made thin film. We employ molecular dynamics simulation using charge-optimized many-body potential (COMB) to perform heating and cooling simulations for different thicknesses of the hafnia layer. Our results suggest that, during heating, as the annealing temperature increases, the severity of delamination decreases. At extremely low thickness of the hafnia layer, delamination does not occur. However, significant delamination is observed during the cooling process, especially when the high temperature gradient is high.

Modeling the impact of incomplete conformality during atomic layer processing

Atomic layer processing (ALP) is a modern fabrication technique for the deposition or etching of materials, which provides precise control of film thickness, composition, and conformality on a nanometer scale. This makes it crucial for the fabrication of high aspect ratio (HAR) structures, such as 3D NAND memory stacks, as its self-limiting nature provides enhanced conformality compared to traditional processes. However, as the number of NAND stacks grows and the aspect ratio continues to increase, deviations from full conformality can often occur due to precursor desorption from the surface. In this regard, a model for surface coverage during ALD in the presence of desorption, leading to incomplete conformality, has been developed and implemented in process simulation frameworks. This work is an extension of our previous research which concentrated on developing an accurate modeling approach for ALD in HAR structures (L.Aguinsky et al., Solid State Electron. 201, 2023). The model combines existing Knudsen diffusion and Langmuir kinetics methods and includes the Bosanquet formula for gas-phase diffusivity and reaction reversibility. It has been incorporated into academic and commercial level-set-based topography simulators. The parameters for the model have been calibrated using published results for the ALD of Al2O3 from trimethylaluminum (TMA) and H2O in HAR geometries. The temperature dependence of the H2O step is likewise analyzed, revealing an activation energy of 0.178eV, which is consistent with recent experiments. In the TMA step, the Bosanquet formula leads to improved accuracy, and the same parameter set is able to reproduce multiple experiments, demonstrating that the model parameters accurately capture reactor conditions. Finally, the developed model is combined with atomic layer etching (ALE) to simulate the controlled, conformal deposition of HfO2 inside HAR 3D NAND structures.

Preventing oxide precipitation in selective wet etching of Si3N4 for 3D-NAND structure fabrication: The role of bubbles

Selective wet etching of Si3N4 is a critical process in the fabrication of 3D-NAND structures; however, it faces a oxide precipitation problem that significantly deteriorates the remaining structure morphology. A recent study by Kim et al.(Kim et al., 2022 [1]) showed that generating CO2 bubbles during the wet etching process efficiently solves the precipitation problem in the fabrication of a 128 multi-layer 3D-NAND structure. In this study, we numerically investigated the multiscale diffusive transport of oxides in the etching process via three different simplified simulations at different scales to reveal the underlying mechanism. We found that mass transport within the multilayer structures alone cannot contribute to the oxide precipitation behavior. Macroscopic transport from the wafer-etchant interface to the bulk must be considered since it contributes to a high oxide concentration at the wafer-etchant surface, which further increases the concentration within the trenches, leading to the precipitation problem. Through the conjecture oxide transport simulation, we found that the large bubbles generated from the reaction agitate the surrounding liquid and dramatically reduce the oxide concentration at the wafer-etchant surface by one order of magnitude, thereby solving the precipitation problem. Our findings clearly explain the experimental results reported by Kim et al. and will further benefit the development of process-intensification technologies in wet etching.

Behavior of oxide regrowth during the selective Si3N4 etching process on 3D NAND structures using finite element computational simulations

Oxide regrowth should be suppressed during the etching of silicon nitride, which is used to fabricate three-dimensional Not AND (3D NAND) devices. This requires a detailed understanding on the mass-transfer characteristics of Si3N4 etching byproducts that cause oxide regrowth. Finite element method (FEM) simulations are performed to investigate the mass transfer of Si3N4 etching byproducts (EBSi3N4) and oxide regrowth during Si3N4 etching on a 3D Si3N4/SiO2 multistack. In particular, the concentration profiles of the byproducts under various etching conditions, such as different numbers of Si3N4/SiO2 multistacks, diffusion coefficients of the byproducts, etching rates of Si3N4, and initial concentrations of Si-based additives, are monitored. Furthermore, the in-situ generation of oxide regrowth under various etching conditions is evaluated. Consequently, an increase in the diffusion coefficient of the byproducts is proposed as the most promising method for suppressing oxide regrowth during Si3N4 etching on high-numbered 3D NAND stacks. The FEM simulation results are strongly supported by data from Si3N4 etching experiments on Si3N4/SiO2 multistacks.

Selective Si<sub>3</sub>N<sub>4</sub> Etching for 3D NAND Integration by Using Low Concentration of H<sub>3</sub>PO<sub>4</sub>

This study investigated the etching kinetics of Si3N4 in various concentration of H3PO4 solution and the effect of Si3N4 etching enhancers on the etching process, particularly for 3D NAND trench structures. 30 wt% H3PO4 was used to etch Si3N4, which can produce higher Si3N4/SiO2 etching selectivity and similar Si3N4 etching rate compared to a conventional 85 wt% H3PO4. 30 wt% H3PO4 showed significantly improved etching performance for the Si3N4/SiO2 3D NAND structure as compared to 85 wt% H3PO4. In particular, the transportation ability of H3PO4 into 3D NAND trench structures can be improved by reducing viscosity of etchant, which can be obtained by reducing the concentration of H3PO4. In addition, Si3N4 etching enhancers were introduced to accelerate the Si3N4 etching kinetics in 30 wt% H3PO4. Addition of such additives improved the Si3N4 etching rate and Si3N4/SiO2 etching selectivity while suppressing oxide regrowth. The results provide valuable insights for optimizing selective Si3N4 etching process in 3D NAND structures.

Investigation of Oxide Regrowth in the Selective Si<sub>3</sub>N<sub>4</sub> Etching Process for 3D NAND Fabrication by Using Finite Element Modeling Simulation

In the process of manufacturing three-dimensional Not AND (3D NAND) flash memory devices, oxide regrowth occurs during the selective Si3N4 etching process on the Si3N4/SiO2 multi-stack structures. The oxide regrowth issue must be suppressed. Thus, effects of two factors, the mass transfer ability of etching byproduct and the stack number of 3D NAND structure, on oxide regrowth were investigated in this study using finite element method (FEM) simulation. Using FEM simulation, we predicted that increase in the stack number of the 3D NAND structure and decrease in the diffusivity of Si3N4 etching byproducts highly aggravated the oxide regrowth. Therefore, it was suggested that an etchant capable of promoting H2SiO3 diffusion behavior would inhibit the oxide regrowth during the selective Si3N4 etching process of the 3D NAND structure.

Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages.

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height.

A Novel Structure to Improve the Erase Speed in 3D NAND Flash Memory to Which a Cell-On-Peri (COP) Structure and a Ferroelectric Memory Device Are Applied

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through a pillar in the P+ crystal silicon sub-region located at the bottom of the 3D NAND flash structure to which the COP structure is applied. To verify this, we first confirmed that when the Gate Induced Drain Leakage (GIDL) erasing method used in the 3D NAND structure using the existing Charge Trap Flash (CTF) memory is applied as it is, the operation speed takes more than 10ms, for various reasons. Next, as a result of using the SP structure to solve this problem, even if the conventional erasing method was used until the thickness of the pillar was 20 nm, thanks to the rapidly supplied hole carriers, a fast-erasing rate of 1us was achieved. Additionally, this result is up to 10,000 times faster than the GIDL deletion method. Next, it was confirmed that when the pillar thickness is 10 nm, the erase operation time is greatly delayed by the conventional erasing method, but this can also be solved by appropriately adjusting the operating voltage and time. In conclusion, it was confirmed that, when the proposed SP structure is applied, it is possible to maximize the fast operation performance of the ferroelectric memory while securing the biggest advantage of the 3D NAND flash structure, the degree of integration.

Control of etch profiles in high aspect ratio holes via precise reactant dosing in thermal atomic layer etching

Thermal atomic layer etching (ALE) was studied in HfO2-based 3D NAND test structures with an aspect ratio of more than 50:1. Etching was performed via ligand exchange with dimethyl-aluminum chloride (DMAC) after surfaces had been fluorinated with hydrogen fluoride (HF). In these 3D NAND structures, we found that the horizontal etch rate of HfO2 as a function of depth (depth loading) depended on the DMAC dosing but was nearly independent of the HF dose. The HF dose and the process pressure were keys to increasing the overall etch amount per cycle. With the highest tested HF dose of 192 Torr s and a total process pressure of 8 Torr, we achieved a uniform etch amount of 0.6 nm per cycle. In addition, we investigated the impact of film quality and film coating conformality in these structures on the depth loading in the succeeding ALE processes. The type of precursor, precursor dosing, deposition rate, and substrate temperature played a fundamental role in controlling the film quality and conformality of the deposited HfO2 layers inside high aspect ratio holes. Fluorination studies on blanket films revealed that fluorination efficiency is improving for pressures in the Torr range compared to previous milliTorr experiments and that only temperatures above 250 °C increased the fluorine concentration in HfO2 significantly, whereas fluorine levels were unchanged between 150 and 250 °C.

Sio2 Surface Passivation Using Aromatic Carboxylic Acid-Added H3po4 Solutions for the Selective Si3n4 Etching of 3d Nand Structures

Sio2 Surface Passivation Using Aromatic Carboxylic Acid-Added H3po4 Solutions for the Selective Si3n4 Etching of 3d Nand Structures

Understanding the Role of Concentrated Phosphoric Acid Solutions as High-Temperature Silicon Nitride Etchants

The ongoing demands for increased storage capacity flash memory in 2D-NAND structures resulted in their replacement by more advanced 3D-NAND structures, with the memory cells made of multiple, vertically stacked silicon oxide/silicon nitride layers. A critical step is selectively etching the silicon nitride films involving a wet etch technique using concentrated phosphoric acid at high temperatures. Concentrated phosphoric acid solutions demonstrate unique behaviors and have particularly high electrical conductivity, but the etching mechanism remains poorly understood. This study investigates the fundamental role of phosphoric acid in the silicon nitride etching and proposes complex active species for the silicon nitride surface protonation and hydroxylation. Characterization methods include 31P-NMR, XPS, FTIR, conductometry, viscometry and ellipsometry. We conclude that the unique performance of concentrated phosphoric acid as silicon nitride etchant results from an anomalously fast proton transport via the Grotthuss diffusion mechanism based on an intramolecular proton transfer driven by easily polarizable, hydrogen bond rearrangements between dissociated molecules as dimers, trimers and triple ions. By contrast, dilute phosphoric acid solutions and other strong protic acids (methanesulfonic acid, sulfuric acid, nitric acid), at both high and low concentrations exhibit protonic conductivity based on molecular diffusion of the H3O+/H2O/anions as separate entities (classical vehicle mechanism).

Thermal Isotropic Atomic Layer Etching of Metallic Molybdenum

In high aspect ratio structures such as 3D NAND stacks, high-k oxides or certain metals need to be removed from sidewalls and even non-line-of-site locations where access via reactive ion etching would be challenging or impossible. To achieve etching in these locations, thermal processes need to be applied that lack any intrinsic directionality and are therefore isotropic. Thermal Atomic Layer Etching is one option to facilitate this kind of process. Therefore, it has gathered significant attention recently and is now being explored in academia and industry.In this work, we demonstrate isotropic Atomic Layer Etching on metallic molybdenum using a three-step process that involves oxygenation of the metal surface, a conversion reaction using boron-trichloride followed by a hydrogen-fluoride clean step. We measured the etch rate per cycle to be around 10 Å with low temperature dependence in the range between 150°C and 250°C.Furthermore, we examined the effectiveness of various oxygenation methods on the surface of metallic molybdenum films. These methods included thermal oxygenation as a function of temperature, oxygenation by a remote plasma and in-situ plasma fluorination. We established that an oxygenation level of more than 70% as measured with XPS is needed in order for the ALE process to work. Levels in this range could be achieved via in-situ plasma oxygenation as well as with a remote plasma. Thermal oxygenation, on the other hand, required substrate temperatures in access of 400°C to oxygenate at the 70% level.In this study we also show an example of molybdenum ALE in an application that involved the removal of this metal from a 50:1 aspect ratio 3D NAND structure. We measured etch rates on vertical and horizontal surfaces as well as the depth dependence in removal rate of molybdenum.

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

Implementation of Data Search in Multi-Level NAND Flash Memory by Complementary Storage Scheme

We develop a novel scheme to realize data search in NAND flash memories, which is important for a wide variety of applications in data centers. In our design, the pair unit consists of double neighbor cells in the NAND string, one “data cell” and one “complementary cell”. The NAND string will be at the “Pass” state only when the searching data are completely matched with the stored data. Parameters that affect data search performance are analyzed systematically. Based on simulations in vertically stacked 3D NAND structures, it is shown that the bit-line current ratio of the fully matched case to the worst case of one mismatched data is more than ~104 in both MLC (multi-level cell) and TLC (triple-level cell) modes, and ~102 can still be obtained in QLC (quad-level cell) mode after read voltage optimizations. These results indicate that the proposed scheme is effective for data search in multi-level NAND flash memories and also friendly for peripheral circuits design.

Oxide regrowth mechanism during silicon nitride etching in vertical 3D NAND structures

It is essential to selectively etch Si3N4 in the presence of SiO2 during the process of fabricating vertical 3D NAND structures. SiO2 etching inhibitors can be added to H3PO4 to increase Si3N4-to-SiO2 etch selectivity; however, the addition of SiO2 etching inhibitors to H3PO4 generates oxide regrowth issues on the SiO2 etch stop layers of the Si3N4/SiO2 pair-layer stacks. It is also observed that generation rate of Si3N4 etching byproduct as well as addition of SiO2 etching inhibitor strongly affects oxide regrowth behavior on the Si3N4/SiO2 multipair-layered structure. In addition, the limited mass transfer of Si3N4 etching byproduct produced heavier amounts of oxide regrowth on the corners of the SiO2 etch stop layers and at the stack structure bottoms. Modification of surface reactivity and the adhesion properties of silica-like monomers on the SiO2 etch stop layer may be important factors for reducing oxide regrowth during the selective etching of Si3N4.

Effect of SiO2 Etching Inhibitor to H3PO4 for the Selective Si3N4 Wet Etching of 3D NAND

As the number of stacked layers of the 3D NAND structure increases, the memory density of 3D NAND flash memory device increases [1]. In the fabrication of 3D NAND device, it is essential to selectively etch Si3N4 by an etchant flowing along a narrow slit followed by metal deposition. However, as the number of Si3N4/SiO2 multi-stack increases, selective etching of Si3N4 becomes difficult. In order to increase the Si3N4-to-SiO2 etch selectivity, SiO2 etching inhibitor should be added to H3PO4. Unfortunately, most of SiO2 etching inhibitors added to H3PO4 generate oxide regrowth around SiO2 layer on the Si3N4/SiO2 multi-stack structure. In this study, the mechanism of oxide regrowth occurred on the 3D NAND structure was investigated. Patterned Si3N4/SiO2 multi-stack structures were prepared. Etching experiments were performed using coupon wafers in 85% H3PO4 or etching inhibitor-added H3PO4 at 160 °C. The Si3N4 and SiO2 etching rates and Si3N4-to-SiO2 etch selectivity were measured using spectroscopic ellipsometry and oxide regrowth on the Si3N4/SiO2 multi-stack structure was analyzed using FE-SEM and HR-TEM. When the Si3N4/SiO2 multi-stack structure was etched in the SiO2 etching inhibitor-added H3PO4, oxide regrowth was observed on the SiO2 layered trenches on the Si3N4/SiO2 multi-stack structure, as shown in Fig. 1. The oxide regrowth occurred intensively at the corner of SiO2 layered trench and oxide regrowth occurred heavily at the bottom of Si3N4/SiO2 multi-stack structure as compared to the top. The overall amount of oxide regrowth on the SiO2 layered trench increased as the concentration of SiO2 etching inhibitor added to H3PO4 increased. In addition, it is shown that generation rate of etching product is an important factor to occur oxide regrowth. Based on the results, it is suggested that etching inhibitor addition and high generation rate of etching product and mass transfer limitation are responsible for the oxide regrowth. Through their optimization, selective Si3N4 etching on the Si3N4/SiO2 multi-stack structure without oxide thinning and regrowth could be obtained, as shown in Fig. 2.

Deposition profile of ammonium bromide in N2/HBr plasmas for high-aspect-ratio multilayer etching

The deposition profile of ammonium bromide in N2/HBr plasmas was evaluated as a function of depth in a macro-cavity structure for the high-aspect-ratio etching process. The macro cavity reproduces deep holes in 3D NAND structures. The profile was compared with the calculated results of that of fluorocarbon (FC) in CF2 radicals. The decay in the ammonium bromide deposition is smaller than that of FC over a depth of 50 mm in the cavity. The 50 mm depth corresponds to an aspect ratio of 60. To clarify the experiment, two models were investigated; ammonium bromide forms in the gas phase, and on a solid surface, respectively. It was found that the latter model reasonably clarifies the experiment when comparing the two models. These results imply that ammonium bromide sufficiently reaches the bottom of deep holes in 3D NAND high-aspect-ratio structures.

Representative volume element analysis for wafer-level warpage using Finite Element methods

Wafer warpage of semiconductors in the manufacturing process is severe problem that decreases the quality and productivity. As the 3D NAND flash was developed, warpage became more important because the stack height increased. Some researches were carried out to expect the warpage using simulation. However, most studies have focused on the wafer-level regardless of the 3D NAND structures. It is very difficult to study the warpage with 3D NAND structures due to the inherent complexity. This paper presents simulation techniques to analyze warpage of the wafer-level. Equivalent material properties were obtained by using Representative Volume Element (RVE) model in this simulation. Wafer-level warpage predictions were analyzed and verified by comparing to experiment results. Finally, a sensitivity analysis was conducted to find the dominant factors affecting warpage. From this analysis, Young's modulus and thermal expansion coefficient were determined as dominant parameters of wafer warpage

Silica Formation during Etching of Silicon Nitride in Phosphoric Acid

The etching of silicon nitride using phosphoric acid with silicon dioxide as a mask is an important process step used in the production of 3D NAND devices. This paper examines the theory of formation of a silica film onto the silicon dioxide surface during this etching step by performing a shell balance analysis of silica species in the etched out liquid volume of the 3D NAND structures. The method of moments is used to solve for the moments of the distribution of particle sizes, and this is used to solve for the potential energy barrier for silica particles to adhere to the silicon dioxide surface.