3D Microelectronic Packaging Research Articles

Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review.

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency.

A boundary element procedure to analyze the thermomechanical contact problem in 3D microelectronic packaging

The interface between two surfaces in contact is formed by numerous microcontacts and gaps separating both surfaces. The heat flow from one surface to the other has to overcome these gaps by means of a thermal contact resistance. In microelectronic packaging it is necessary to evacuate the heat from the microprocessor, so it is important to have a great conductance of the heat flow between the microprocessor and the heatsink. This work studies the 3D microchip-heatsink contact in microelectronic packaging using the boundary element method. The formulation includes a variable thermal contact resistance along the contact zone formed in the interfase between the microchip and the heatsink. The thermal contact resistance is a function of the contact normal traction, so the thermal and the thermoelastic problems are coupled. The values of the final thermal and mechanical variables of the boundary of the microelectronic packaging and the thermal contact resistance are obtained by a double iterative schema.

Fabrication and shear strength analysis of Sn-3.5Ag/Cu-filled TSV for 3D microelectronic packaging

In this study, lead free Sn-3.5Ag solder bumps have been deposited on Cu-filled through-silicon via (TSV) by electroplating method. The solder bumps are plated using an acidic solution composed of SnSO4, H2SO4, Ag2SO4, thiourea and an additive. The current density is varied from −30 to −60 mA/cm2 to obtain the eutectic Sn-3.5Ag solder. The copper is electroplated in TSV using an acidic solution of CuSO4·5H2O, H2SO4, HCl, and an inhibitor. The bottom-up Cu-filling in TSV is achieved by a 3-step pulse periodic reverse (PPR) electroplating. It has been observed that the eutectic Sn-3.5Ag solder is achieved at a current density of −55 mA/cm2. The solder bumps are further reflowed onto TSV at 260 °C for 20 seconds, and shear strength of the formed Sn-3.5Ag/Cu-filled TSV joint is investigated. The results indicate the formation of Cu6Sn5 and Ag3Sn intermetallic compounds (IMCs) at the joint interface. It is found that with an increase of shear speed from 0.5-10 mm/s, the shear stress initially increases to a maximum, and then decreases beyond shear speed of 10 mm/s through 500 mm/s. It is shown that the ductile fracture mode gradually decreases beyond shear speed of 10 mm/s and disappears completely at 500 mm/s.

Using Synchrotron Radiation Microtomography to Investigate Multi-scale Three-dimensional Microelectronic Packages.

Synchrotron radiation micro-tomography (SRµT) is a non-destructive three-dimensional (3D) imaging technique that offers high flux for fast data acquisition times with high spatial resolution. In the electronics industry there is serious interest in performing failure analysis on 3D microelectronic packages, many which contain multiple levels of high-density interconnections. Often in tomography there is a trade-off between image resolution and the volume of a sample that can be imaged. This inverse relationship limits the usefulness of conventional computed tomography (CT) systems since a microelectronic package is often large in cross sectional area 100-3,600 mm(2), but has important features on the micron scale. The micro-tomography beamline at the Advanced Light Source (ALS), in Berkeley, CA USA, has a setup which is adaptable and can be tailored to a sample's properties, i.e., density, thickness, etc., with a maximum allowable cross-section of 36 x 36 mm. This setup also has the option of being either monochromatic in the energy range ~7-43 keV or operating with maximum flux in white light mode using a polychromatic beam. Presented here are details of the experimental steps taken to image an entire 16 x 16 mm system within a package, in order to obtain 3D images of the system with a spatial resolution of 8.7 µm all within a scan time of less than 3 min. Also shown are results from packages scanned in different orientations and a sectioned package for higher resolution imaging. In contrast a conventional CT system would take hours to record data with potentially poorer resolution. Indeed, the ratio of field-of-view to throughput time is much higher when using the synchrotron radiation tomography setup. The description below of the experimental setup can be implemented and adapted for use with many other multi-materials.

A Review of Failure Analysis Methods for Advanced 3D Microelectronic Packages

Advanced three dimensional (3D) packaging is a key enabler in driving form factor reduction, performance benefits, and package cost reduction, especially in the fast paced mobility and ultraportable consumer electronics segments. The high level of functional integration and the complex package architecture pose a significant challenge for conventional fault isolation (FI) and failure analysis (FA) methods. Innovative FI/FA tools and techniques are required to tackle the technical and throughput challenges. In this paper, the applications of FI and FA techniques such as Electro Optic Terahertz Pulse Reflectometry, 3D x-ray computed tomography, lock-in thermography, and novel physical sample preparation methods to 3D packages with package on package and stacked die with through silicon via configurations are reviewed, along with the key FI and FA challenges.

Synchrotron Radiation Microtomography for Large Area 3D Imaging of Multilevel Microelectronic Packages

3D x-ray computed tomography (CT), using conventional laboratory-based x-ray sources, has been used in the past to image multiple levels of interconnects in 3D microelectronic packages. These conventional x-ray sources can provide high resolution images with throughput times (TPT) of several hours. However, this can only be performed on localized areas of about 1–2 mm2, which gravely limits the application of 3D x-ray CT in the field of microelectronic packages with sizes usually in the range of 100–3600 mm2. An alternative to laboratory-based x-ray sources is synchrotron radiation, which can produce large area collimated beams for high flux x-ray imaging over a much larger field of view (FOV) than conventional sources. Synchrotrons can potentially image an entire 3D stacked chip package at high resolutions in less than an hour. Here, we present results using the micro-CT line at the advanced light source synchrotron to image an entire 16 × 16 mm system in a package in times as low as 3 min, demonstrating several orders of magnitude increase in the ratio of FOV to TPT as compared to laboratory-based x-ray methods.

Integrating Through-Wafer Interconnects With Active Devices and Circuits

Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.