3D IC Research Articles

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

3D alignment of distant patterns with deep-subwavelength precision using metasurfaces

Measurement of the relative positions of two objects in three dimensions with sub-nanometer precision is essential to fundamental physics experiments and applications such as aligning multi-layer patterns of semiconductor chips. Existing methods, which rely on microscopic imaging and registration of distant patterns, lack the required accuracy and precision for the next generation of three-dimensional (3D) chips. Here we show that 3D misalignment between two distant objects can be measured using metasurface alignment marks, a laser, and a camera with sub-nanometer precision. Through simulations, we demonstrate that the shot noise-limited precisions of the lateral and axial misalignments between the marks are λ0/50, 000 and λ0/6, 300 (λ0: laser’s wavelength), respectively. With its high precision and simplicity, the technique enables the next generation of 3D-integrated optical and electronic chips and paves the way for developing cost-effective and compact sensors relying on sub-nanometer displacement measurements.

Low-temperature Cu-Cu direct bonding with ultra-large grains using highly (110)-oriented nanotwinned copper

With the application of Cu-Cu direct bonding technology in high-performance electronic devices, improving bonding reliability is essential for achieving high-density 3D IC integration. In this study, we innovatively applied highly (110)-oriented perpendicular nanotwinned Cu (p-ntCu) to achieve Cu-Cu direct bonding at low temperature and pressure. The anisotropic growth of p-ntCu during annealing at 200 °C resulted in the formation of ultra-large grains, which could improve the conductivity of the electrodeposited Cu film. Two Cu films were bonded at 200–250 °C with 2 MPa pressure for 1 h, and there was almost no void at the bonding interface. Anisotropic grain growth occurred within the bonding joint and grain boundary migration was observed at the bonding interface. The shear strength after bonding at 250 °C was measured as 58.3 MPa on average, indicating a relatively high quality of such Cu-Cu bonding. The p-ntCu can achieve Cu-Cu bonding and improve the conductivity by anisotropic grain growth at low temperature and pressure, which has great potential for Cu interconnect applications.

Thermal spreading in a multilayer geometry with convective cooling along the side wall of each layer

Two-dimensional thermal conduction between a source/sink and a body of larger size results in thermal spreading and constriction, which are of much technological importance in problems such as semiconductor thermal management. While the traditional analysis of thermal spreading and constriction assumed adiabatic side walls, there is growing interest in convective heat removal from the side walls, such as in multilayer three-dimensional integrated circuits (3D ICs) and stacked Li-ion cells in a battery pack. This work presents theoretical analysis of thermal spreading in a multilayer body with distinct convective heat transfer coefficients along the side wall for each layer, in addition to anisotropic thermal conductivity in each layer and thermal contact resistance at interfaces between layers. A series solution for the temperature distributions in each layer is derived, with a unique set of eigenvalues for each layer. A set of linear algebraic equations that govern the coefficients of the series solutions is derived. Results are shown to agree well with past work for special cases, as well as with numerical simulations for general problems. The impact of source size, thermal anisotropy and Biot numbers of various layers is analyzed in detail. In particular, the interplay between Biot numbers along the sidewall and at the sink plane in determining total thermal resistance is investigated in detail. This work contributes towards a fundamental understanding of theoretical thermal conduction in problems of practical relevance, such as advanced microelectronics and Li-ion cells. Results may find application in the design and optimization of these and other engineering systems where thermal spreading or constriction play an important role.

Aging affects the mechanical interaction between microplastics and lipid bilayers.

Plastic pellets, the pre-production form of many plastic products, undergo oxidation and photodegradation upon exposure to oxygen and sunlight, resulting in visible color changes. This study examines the impact of environmental aging on the mechanical interactions between pellet-derived microplastics and lipid bilayers, a critical component of biological membranes. Polyethylene pellets were collected from La Pineda beach near Tarragona, Spain, and categorized by chemical composition and yellowing index, an indicator of aging. The hydrophilicity of these pellets was assessed using contact angle measurements. Microplastics were produced by grinding and filtering these pellets and subsequently dispersed around a free-standing lipid bilayer within a 3D microfluidic chip to investigate their interactions. Our results reveal that aged microplastics exhibit a significantly increased adhesive interaction with lipid bilayers, leading to greater bilayer stretching. Theoretical modeling indicates a linear relationship between the adhesive interaction and the contact angle of the pellets, reflecting their hydrophilicity. These findings emphasize the increased mechanical impact of aged microplastics on biological membranes, which raises concerns about their potential toxicological effects on living organisms. This study highlights the importance of understanding the interactions between environmentally aged microplastics and biological systems to assess their risks, as these may differ significantly from pristine microplastics often studied under laboratory conditions.

Impact of magnetic field variation on thermally annealed tantalum-filled vertical superconducting interconnects for scalable quantum computing systems

Efforts to scale down advanced quantum processors with more numbers of qubits offer challenges since the integration of qubits is a significant obstacle in the path. Superconducting vertical interconnects in 3D IC integration can provide a crucial solution for wiring complexities, as shorter interconnections reduce energy loss when working in cryogenic conditions with better signal fidelity. Using the time-dependent Ginzburg–Landau equation, this simulation study analyzes vertical superconducting interconnects filled with materials like tantalum, niobium, and thermally annealed tantalum. It also investigates how London penetration depth (temperature-dependent) and magnetic fields affect Cooper pair density and, consequently, current density.

Microstructure of ternary Sn-Bi-xCu alloy on mechanical properties, current endurance and corrosion morphology via cycling corrosion test

Low melting temperature of Sn-58 wt.% Bi (SB) solders adding 0.5wt.% Cu (SB05C) and 1.7wt.% Cu (SB17C) concentrations were evaluated for the signal transmission in the 3D IC package. Microstructure combined with phase analysis and Pandat simulation were together with to explain the relationship among the mechanical property, electrical endurance and corrosion resistance. By Cu decoration, the presence Cu6Sn5 intermetallic compound (IMC) acts as heterogeneous nucleation sites to reduce surface free energy and generate fine Bi grain that resulted in higher hardness value. The power-law was used to explain the mechanism of interfacial IMC growth, both Cu6Sn5 and Cu3Sn formation were speculated to be volume diffusion control and surface reaction domination, respectively. The fracture morphology by shear testing indicates that earliest plastic deformation accompanied with brittle rupture were major factors due to the intergranular fracture and Cu6Sn5 compound induced bulk fracture. By cycling corrosion test (CCT), the lump shape of SnO2 by-product was found among solders at three cycling. After seven cycling, Sn phase has been completely corroded and Cu6Sn5 IMC began to be corroded forming circle shape of Cu2O but Bi phase still not be corroded among solders. In the electrical endurance, dense Cu6Sn5 dispersed in solder bulk and fine grain size were feasible to induce current crowding and joule heating, thus Cu deteriorated SB solders is easily failed.

Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application

The gate-all-around (GAA) structure avoids the problems inherent in miniaturizing field-effect transistors (FETs), such as off-state leakage current and short-channel effects. Among GAA structures, vertical GAA (VGAA) structures are expected as promising building blocks for future three-dimensional integrated circuit applications. The vertical III-V nanowires (NWs) on Si are expected as the fast channel materials for the VGAA structures on Si platforms. Thus, the combination of the VGAA structure with III-V NWs on Si significantly enhances on-state current while maintaining good gate controllability under low supply voltage. In addition, III-V NWs/Si tunnel junctions, which are formed by the direct integration of vertical III-V NWs on Si, can be utilized as VGAA tunnel FETs (TFETs) for low-power switch. Here we report on direct integration of vertical InGaAs NWs on silicon-on-insulator (SOI) substrates by selective-area growth and demonstrations of InGaAs NW-channel VGAA transistors (FETs and TFETs) on SOI.

Development of a 3D Hydrogel SERS Chip for Noninvasive, Real-Time pH and Glucose Monitoring in Sweat.

Traditional diagnostic methods, such as blood tests, are invasive and time-consuming, while sweat biomarkers offer a rapid physiological assessment. Surface-enhanced Raman spectroscopy (SERS) has garnered significant attention in sweat analysis because of its high sensitivity, label-free nature, and nondestructive properties. However, challenges related to substrate reproducibility and interference from the biological matrix persist with SERS. This study developed a novel ratio-based 3D hydrogel SERS chip, providing a noninvasive solution for real-time monitoring of pH and glucose levels in sweat. Encapsulating the probe molecule (4-MBN) in nanoscale gaps to form gold nanoflower-like nanotags with internal standards and integrating them into an agarose hydrogel to create a 3D flexible SERS substrate significantly enhances the reproducibility and stability of sweat analysis. Gap-Au nanopetals modified with probe molecules are uniformly dispersed throughout the porous hydrogel structure, facilitating the effective detection of the pH and glucose in sweat. The 3D hydrogel SERS chip demonstrates a strong linear relationship in pH and glucose detection, with a pH response range of 5.5-8.0 and a glucose detection range of 0.01-5 mM, with R2 values of 0.9973 and 0.9923, respectively. In actual sweat samples, the maximum error in pH detection accuracy is only 1.13%, with a lower glucose detection limit of 0.25 mM. This study suggests that the ratio-based 3D hydrogel SERS chip provides convenient, reliable, and rapid detection capabilities with substantial application potential for analyzing body fluid pH and glucose.

Evaluation of the novel ALK5 inhibitor EW-7197 on therapeutic efficacy in renal fibrosis using a three-dimensional chip model.

EW-7197, a potent oral ALK5 inhibitor, was assessed for its impact on transforming growth factor beta 1 (TGF-β1)-induced fibrosis in a three-dimensional (3D) renal fibrosis-on-a-chip and a mouse model. The evaluation included tubular epithelial-mesenchymal transition, angiogenesis, and inflammatory cytokine expression. In a 3D renal fibrosis-on-a-chip model, three cell types (kidney fibroblasts, human proximal tubular cell line, and human umbilical vein endothelial cells) were cultured and treated with TGF-β1 and EW-7197. Expression of alpha smooth muscle actin (α-SMA) and keratin 8 (KRT-8) was assessed, angiogenesis was observed via confocal microscopy, and cytokine levels were measured using real-time polymerase chain reaction, immunoassay, and enzyme-linked immunosorbent assay. In a cisplatin-induced renal fibrosis mouse model, blood urea nitrogen levels, TGF-β, and Smad 2/3 were determined, and renal fibrosis was assessed with Masson's trichrome stain. The α-SMA expression was significantly lower in the EW-7197 group than in the TGF-β fibrosis group. TGF-β decreased the expression of the epithelial marker KRT-8, an effect that was reversed by EW-7197 and SB431542. In the TGF-β-induced fibrosis model, the length of the thick vessels was reduced, and the diameter of both thick and thin vessels was decreased, but EW-7197 reversed these effects. EW-7197 significantly reduced the messenger RNA expression of TGF-β and increased the levels of vascular endothelial growth factor receptor 2, interleukin (IL)-10, and IL-6. EW-7197 reduced the levels of secretory cytokines TGF-β1, TGF-β3, IL-1β. In the cisplatin-induced renal fibrosis mouse model, EW-7197 reduced renal fibrosis by down-regulating TGF-β signaling. EW-7197 attenuated the TGF-β1-induced fibrotic cellular response in the 3D chip model and animal model. These findings indicate the potential effect of EW-7197 in attenuating renal fibrosis.

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

A review of physical heat dissipation methods for 3D integrated technology

Three-dimensional integrated circuits have higher integration than two-dimensional integrated circuits, and can obtain higher performance and lower power consumption in a certain space. In order to fulfill higher efficiency, thermal management becomes particularly important in 3D integration technology. However, the traditional heat dissipation method cannot satisfy the heat dissipation needs of three-dimensional integrated circuits, which require better heat dissipation methods to be developed. This paper introduces the realization of three-dimensional integrated circuit using silicon via (TSV) technology, which allows the chip to be vertically stacked to transmit information. This paper summarizes the research methods and findings of three-dimensional integrated circuit heat dissipation in recent years, including thermal through silicon via (TTSV) and microchannel cooling. It also emphasizes the advantages and disadvantages of both mehods, and the challenges faced in current research via an overview. The future research trend for both heat dissipation methods mainly consists of combining special algorithms to achieve thermal-electrical codesign and thermal management of three-dimensional integrated circuits.

Atomic-Scale Investigation of Electromigration Behavior in Cu-to-Cu Joints at High Current Density

Three-dimensional integrated circuit (3D IC) packaging offers significant advantages, such as enhanced computational efficiency through greater integration and shorter interconnection distances. The effective interconnection of layers, particularly through redistribution layer (RDL) technology, is crucial for the successful operation of 3D ICs. While copper remains the preferred material for interconnections, often in conjunction with through-silicon via (TSV) technology for chip-to-chip links, the shrinking dimensions of components present challenges. In particular, the reduction in size may lead to elevated current densities in individual joints, giving rise to issues like electromigration (EM) and potential failure. EM-induced atomic migration may lead to the formation of voids in the interconnection. The accumulation of voids to a critical point may result in an open circuit in the joints, significantly impacting the conductor's reliability. This work delves into the micro-scale aspects of these challenges, complementing previous macroscopic investigations. We aim to elucidate the behavioral mechanisms through atomic-scale observations, employing an in-situ high-resolution transmission electron microscope (in-situ HRTEM) to observe atomic-scale images of EM. The insights gained from this work not only contribute to the academic understanding of industry challenges but hold potential applications in real-world manufacturing processes. Fig. 1. (a) Schematic diagram of TEM sample preparation. (b) Cross-sectional HRTEM image of copper bonding. (c, d) TEM images showing voids expansion at bonding interface. Figure 1

Enhanced Mechanical Properties with Ag Addition in Electroplated Ni-Sn Solder Joints: Sub-10 Micron Bond Thickness

Keywords: Micro-bump; Microstructure; Intermetallic compounds; Mechanical properties; thermocompression bondingThe advancement of electronic devices has garnered more extensive attention towards three-dimensional integrated circuit (3D-IC) technology due to microbump size reduction and increased power density. Microbumps play an important role in driving the development of this technology, especially in 3D chip-stacking involving multiple reflow processes. The reduction in microbump height spotlights the presence of intermetallic compounds (IMCs). In comparison to traditional ball grid array (BGA) solder joints, microbumps with smaller solder volumes exhibit a predominant fraction of IMCs at solder joints, especially with microbump dimensions potentially shrinking to less than 10 micrometers.The interface reaction within confined spaces has become a critical concern. Mechanical properties will be dominated by IMC properties rather than solder characteristics. In conventional Cu/Sn/Cu solder joints, grain coarsening and prolonged reflowing times, which result in IMC collisions from opposing substrates, forming columnar grains with a uniform orientation, make the solder joint less reliable. Furthermore, the Cu3Sn layer in Cu/Sn/Cu microbumps presents another challenges, indicating the formation of Kirkendall voids, increasing the risk of brittle interface fractures.This study investigates the mechanical reliability and microstructure of two sub-10um sandwiched structures: Cu/Ni/Sn/Ni/Cu and Cu/Ni/Sn-3.5Ag/Ni/Cu. In the 3D-IC manufacturing process, solder joints will experience multiple reflow processing. Different reflow heat treatment process to achieve different fractions of Ni3Sn4 IMCs were performed on both sandwiched structure. Despite the formation of internal voids due to volume shrinkage in Ni/Sn solder joints, the addition of silver in the solder, forming Ag3Sn, effectively fills these voids. The long-time reflowed sample showed outstanding mechanical properties via the addition of silver in solder. In this study, the influence of silver addition on the microstructure and mechanical properties of the overall joints under identical reflow conditions, the fracture path observation after shear test were investigated. The growth mechanism of Ag3Sn and its distribution in the solder would be further explored and addressed. Figure 1

Next Generation Heterogeneous 3D IC Chip Packaging

The demand for a faster and more efficient IC has been steadily increasing more than ever to accommodate the trend of Artificial Intelligence, Industry 4.0, Machine Learning, and Big Data. Traditionally, the semiconductor industry has kept up with demand of faster and more efficient IC by shrinking the size of transistor. As we approach a 1 nm transistor the technological challenge will be challenging to overcome as quantum tunneling becomes more pronounced and would decrease the reliability of the chip. To overcome this technological challenge, an advance packaging of 3D IC chip technology has been developed and delivered to market such as CoWoS (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out). However, the aforementioned technology have their drawbacks with CoWoS uses interposer and TSV (through-silicon substrate via) which make it costly, time consuming, and wastes a lot of energy and InFO is limited in the number of layers it can accommodate for chiplets. Both of those technology are currently limited to 2 or 3 layer of IC and difficult to be modularize. In this study, we aim to develop a heterogeneous 3D IC package that can overcome the aforementioned problem which is modular, cost-effective, able to integrate chip from different manufacturers, and capable to stack more than 3 layers of ICs. This study has successfully completed the first stage of development by employing an advanced package consisting of Epoxy substrate with 200Å Ti/500Å Pt/1000Å Au metal interconnects, previously fabricated as a base for 3D stacking. Keywords : 3D IC Package, Advance Packaging, Modulable IC Packaging, Heterogeneous Integration Figure 1

Hybrid Bright-Dark-Field Microscopic Fringe Projection System for Cu Pillar Height Measurement in Wafer-Level Package.

Cu pillars serve as interconnecting structures for 3D chip stacking in heterogeneous integration, whose height uniformity directly impacts chip yield. Compared to typical methods such as white-light interferometry and confocal microscopy for measuring Cu pillars, microscopic fringe projection profilometry (MFPP) offers obvious advantages in throughput, which has great application value in on-line bump height measurement in wafer-level packages. However, Cu pillars with large curvature and smooth surfaces pose challenges for signal detection. To enable the MFPP system to measure both the top region of the Cu pillar and the substrate, which are necessary for bump height measurement, we utilized rigorous surface scattering theory to solve the bidirectional reflective distribution function of the Cu pillar surface. Subsequently, leveraging the scattering distribution properties, we propose a hybrid bright-dark-field MFPP system concept capable of detecting weakly scattered signals from the top of the Cu pillar and reflected signals from the substrate. Experimental results demonstrate that the proposed MFPP system can measure the height of Cu pillars with an effective field of view of 15.2 mm × 8.9 mm and a maximum measurement error of less than 0.65 μm.

Design of Silicon Core Coaxial TSVs to Reduce Crosstalk Effects for 3D IC Applications

This paper presents the effectiveness of the copper (Cu)-based coaxial through silicon vias (CTSVs) to reduce crosstalk noise and propagation delay. In the proposed CTSVs, the polymer liners are used as insulating material which cancels the crosstalk functional failures. The impacts of the proposed CTSVs on the electrical performance are noticed for different parameters and properties of the material. Simulations of the proposed CTSVs are executed using the standard HSPICE and SYMICAD tools. The results indicated that the effects of crosstalk are reduced using the polymer liners instead of silicon dioxide (SiO2) liners in the proposed CTSVs. The electrical performances of the proposed CTSVs are investigated for various thicknesses of Cu and BCB. Furthermore, a comparative study has been carried out for the SiO2 and benzocyclobutene (BCB) liners. It is observed that BCB liner-based CTSVs crosstalk noise and delay values are reduced by up to 25.06% and 27.8% compared to the SiO2 liner-based TSVs.

Preface

The 2024 4th International Conference on Advanced Materials and Mechatronics (ICAMM 2024) was held via virtual form in Xi’an, China from May 10th to 12th, 2024. Previous conferences in the past three years of this series have been successfully held and it was agreed to hold the conference once a year, with the aim to establish and develop a constant international collaboration. In recent years, interest in advanced materials and mechatronics has been flourishing all over the globe due to both theoretical and practical requirements. Considering the trend, the fourth conference of ICAMM series was organized in order to provide an international academic forum for developing research cooperation and to promote research and other academic activities in related fields. We entertained about 80 participants at ICAMM 2024 and arranged various speeches and presentations which cover a wide range of topics related to the Conference theme. Many scholars and researchers all over the world have contributed to the emerging technology and application of advanced materials and mechatronics. The wonderful keynote speeches included Semiconductor Lighting and Display: Design and Manufacturing Technology for High Efficiency GaN-based LED Chips (by Prof. Shengjun Zhou, Wuhan University, China), Materials, Processing and Reliability of Low Temperature Bonding in 3D Chip Stacking (by Prof. Liang Zhang, Xiamen University of Technology, China), Monitoring Applications of Electronic Devices in the Shipbuilding Industry (by Assoc. Prof. Fengming Du, Dalian Maritime University, China), and Addictive Manufacturing and Intelligent Processing Control of Advanced Metal Materials (by Prof. Kun Li, Chongqing University, China). ICAMM 2024 has been endorsed and supported by many national and international engineering-related universities and organizations and was a complete success. The topics of papers collected and undergone rigorous peer review in the Proceedings of ICAMM 2024 can be classified as follows: Semiconductor Materials, Mechanics of Materials, Material Forming Process and Equipment, Advanced Electromagnetism, Laser Physics and Technology, Irradiation electronics, etc. Last but not the least is our gratitude. We would like to express our sincere thanks to all the keynote speakers, authors, committee members for the success of the Conference, which has given rise to this present volume of selected papers. We would also like to acknowledge the staff of Journal of Physics: Conference Series for their effective work to make this Proceedings published. The Committee of ICAMM 2024 List of Committee Member is available in this Pdf.

New Computational Methods for Enhancing Reliability Testing of Interconnects in 3D ICs: Advanced Algorithms, Optimization Techniques, and Real-World Applications

New Computational Methods for Enhancing Reliability Testing of Interconnects in 3D ICs: Advanced Algorithms, Optimization Techniques, and Real-World Applications

Thermal Modeling and Analysis of 3D ICS with Heat Dissipation Effect of Power Distribution Networks

Thermal Modeling and Analysis of 3D ICS with Heat Dissipation Effect of Power Distribution Networks