3D DRAM Research Articles

Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

This paper concerns appropriate 3D DRAM architecture design and the potential of using 3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM integrated computing systems. We first present a coarse-grained 3D partitioning strategy for 3D DRAM design that can well exploit the benefits provided by 3D integration without incurring stringent constraints on through-silicon via (TSV) fabrications. Targeting multi-core processors, we further present design techniques that can effectively reduce the access latency of 3D DRAM L2 cache, hence improve the overall 3D integrated computing system performance. The effectiveness of these developed design techniques have been successfully evaluated based on CACTI-based memory modeling and full system simulations over a wide spectrum of multi-programmed workloads. Simulation results show that the proposed heterogeneous 3D DRAM design can improve the harmonic mean IPC by 23.9% on average compared with a baseline scenario using 3D DRAM only as the main memory.

Advances in 3D Memory and Logic Devices

Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D DRAM will be presented along with the plans (and possibly some results) of further integration with other 3D host logic devices. Additionally, results from several other recent 3D integrations will be reviewed.

3D DRAM Design and Application to 3D Multicore Systems

From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture.

3D DRAM in Server Application

Server system requirement drives the evolution of 3D DRAM technologies. The new generation provides form factor, electrical and power performance benefits. Meanwhile it brings in a more complicated design, new assembly technologies and new failure mechanisms. The optimum 3D DRAM technology is determined by complex tradeoff of benefits, cost, time to market and reliability. The characteristics of the optimum 3D DRAM technology for DDR2, DDR3 and future server memory system are analyzed in detail. TSV (Through Silicon Via) DRAM array stacking is expected to bring superior power performance which could be a significant market diver. The tradeoff of this future technology and process development trend is presented.

3D-Stacked Memory Architectures for Multi-core Processors

Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examined the performance benefits of such an approach, but all of these works only consider commodity 2D DRAM organizations. In this work, we explore more aggressive 3D DRAM organizations that make better use of the additional die-to-die bandwidth provided by 3D stacking, as well as the additional transistor count. Our simulation results show that with a few simple changes to the 3D-DRAM organization, we can achieve a 1.75x speedup over previously proposed 3D-DRAM approaches on our memory-intensive multi-programmed workloads on a quad-core processor. The significant increase in memory system performance makes the L2 miss handling architecture (MHA) a new bottleneck, which we address by combining a novel data structure called the Vector Bloom Filter with dynamic MSHR capacity tuning. Our scalable L2 MHA yields an additional 17.8% performance improvement over our 3D-stacked memory architecture.

The Stacked Capacitor DRAM Cell and Three-Dimensional Memory

The author chronicles the development of the stacked three-dimensional (3D) DRAM cell, highlighting his role in solving the problems of memory data-bandwidth and forecasting a dramatic increase in memory capacity based on his current work using super-chip integration technology.