8-bit Carry-lookahead Adder Research Articles

A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic

Adders are critical to the efficiency of arithmetic circuits in battery-powered electronic devices. This study demonstrates an 8-bit CLA (carry look-ahead adder) using single-phase ANT logic to increase the computation speed and reduce the power dissipation simultaneously. The single-phase ANT has no internal loop that optimizes the efficiency of the prior ANT. Utilizing a TSMC 40-nm technology, the proposed 8-bit CLA is fabricated. It attains the highest operating frequency of 3.2 GHz and the lowest normalized PDP (power delay product) by on-silicon measurement for 20 pF load.

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors. Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.

Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit

This paper presents a novel energy efficient logic called Charge Sharing Improved Pass Gate Adiabatic Logic (CSIPGL) operating using four phase power clock sources. The CSIPGL based circuit is capable of operating through a wider range of frequency from 100MHz to 1GHz. CSIPGL logic has been designed using UMC 90nm technology model files and are simulated using Cadence® Virtuoso EDA tools. Efficiency of CSIPGL circuit is validated by comparing it against CSSAL, SQAL, SyAL, adiabatic logic circuits based on single charge sharing transistor [14] and EE-SPFAL circuit designs. Power consumption of AND/NAND and XOR/XNOR sub modules used in the design of 4-bit Carry Lookahead Adder circuits (CLA) are compared. 4-bit CLA is taken as a benchmark circuit to validate the efficiency of the proposed CSCPAL circuit.

An adiabatic superconductor 8-bit adder with 24kBT energy dissipation per junction

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this paper, we conducted the high-frequency operation and energy measurement of an AQFP circuit with more than 1000 Josephson junctions in the experiment. We designed an 8-bit carry look-ahead adder (CLA) using AQFP gates and fabricated it using an advanced fabrication technology, the AIST 10 kA/cm2 Nb high-speed standard process. The correct operation of the 8-bit CLA was demonstrated at a 1-GHz clock frequency for a critical carry propagation test vector. The energy dissipation of the 8-bit CLA was measured by observing the power of excitation current. Our results showed that the energy dissipation per operation of the 8-bit CLA can be estimated to be approximately 1.5 aJ, or 24kBT per junction, where kB is the Boltzmann constant and T is the operating temperature.

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.

Dual Recycled Charge Power Gating For Retaining Data and Saving Leakage

Objectives: To innovate power gating technique which is used to recycle charge lost at moment from active to sleep mode by both PMOS header and NMOS footer. Methods: Three 32-bit Carry Look Ahead (CLA) adder circuits and ISCAS-85 benchmark circuits are compared in retention mode including the conventional power gating, single recycled charge power gating, dual recycled charge power gating in term of the power consumption using the 45 nm Predictive Technology Model. A fair timing comparison also is considered in this work. Findings: This proposed 32-bit CLA adder can reduce the standby leakage power consumption up to 60% and 53% in short and long sleep time, respectively, compared to the conventional power gating. Compared to the single recycled charge, the proposed saves up to 25% in short sleep time and 44% in long sleep time. The proposed 32-bit CLA adder is simpler in controlling the circuit in active mode and retention mode. The ISCAS-85 benchmark circuits are also applied to make conclusion in term of saving leakage power consumption. Application: This proposed leakage reduction technique is promising candidate for optimizing more leakage dissipation in digital circuits. Keywords: Charge Recycling, CLA Adder, Leakage Current, Low Power, Power Gating

A Novel Nanometric Parity-Preserving Reversible Carry-Lookahead Adder

ABSTRACTDuring recent years, reversible logic received important attention in cryptography, optical processing, quantum computing, and nanotechnology. Among the reversible computation units, the adder unit is considered the most fundamental computation unit to build a quantum computing system. Due to its low latency, the reversible carry-lookahead adder is mostly used and considered. Parity preserving is also one of the oldest methods for error recognition in digital systems. In this article, we offer new proposals for the nanometric parity-preserving reversible 2-bit carry-lookahead adder. Compared with previous designs, we will demonstrate that our designs would be optimal in the number of garbage outputs, constant inputs, and quantum costs. In order to design circuits at a higher level, we also offer new proposals for the nanometric parity-preserving reversible 4-bit carry-lookahead adder. Since previous proposals that were presented as 4-bit did not have the reversible parity-preserving property, we proceeded with our research.

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.

Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.

Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.

Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits

Low-power, compact, and high-performance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nanotube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MOSFET (CN-MOSFET) domino logic, and CN-MOSFET NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS adder is reduced by 35.53%, 77.96%, and 15.52% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino adders, respectively. Miniaturization of the CN-MOSFET NP dynamic CMOS circuit reduces the dynamic switching power consumption by 80.54%, 95.57%, and 25.66% as compared to the Si-MOSFET domino, Si-MOSFET NP dynamic CMOS, and CN-MOSFET domino circuits, respectively. Furthermore, the CN-MOSFET NP dynamic CMOS adder provides up to 99.98% savings in leakage power consumption as compared to the other adder circuits that are evaluated in this study.

Design and Implementation of Low Power 8-bit Carry-look Ahead Adder Using Static CMOS Logic and Adiabatic Logic

Addition forms the basic structure for many processing operations like counting, multiplication, filtering etc. Adder circuits that add two binary numbers are of great interest for many designers. The simplest approach to design an adder is to implement gates to yield the required logic function. Carry-look ahead adder is a major functional block in arithmetic logic unit due to its high speed operation. The arithmetic logic unit has been widely used in microprocessor systems and mostly in processing modules of embedded systems. Therefore, it is of interest to study the functional behavior and power consumption carry-look ahead adder. In this project, the adder is implemented using 180 nm CMOS technology on bulk substrate. Two logic families i.e. static CMOS and adiabatic logic have been analyzed and implemented to study the transient characteristics of the adder. Finally the power consumption is estimated and compared. From the results it has been found that the static CMOS logic offers low delay whereas the adiabatic logic consumes low power.

Reduced Complexity Hybrid Ripple Carry Lookahead Adder

In this paper we discuss Hybrid Ripple Carry Lookahead Adder (HRCLA), which is a hybrid between Carry Lookahead Adder (CLA) and ripple adder (RA). In HRCLA time is traded off for area and power. HRCLA has been designed by rippling the last carry bit of a 4-bit CLA. HRCLA extracts the traits of Carry Lookahead Adders (CLA) speed and ripple adders (RA), area. A four bit proposed HRCLA has been implemented in Cadence using 45nm technology; the implementation results showed 12.2 %Area, 4.6 % power improvement and 14.01 % critical path delay overhead over CLA.

Constant Delay Logic Style

A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-Vt) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.

Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection

A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The analysis of the area (transistor count) tradeoff is also provided in this work. The output of the addition of two 8-bit binary numbers is done in two cycles. The proposed power-aware pipelining design methodology using a simple data transition detection circuit takes advantage of shutting down the processing stages with identical inputs in two consecutive cycles. The data transition detection circuit is used to monitor the state switching of input data. Not only is it proved to be also suitable for long adders, the power consumption is drastically reduced by at most 50% at every process corner.

A 1.25 ghz 32-bit tree-structured carry lookahead adder using modified ant logic

In this work, a 32-bit tree-structured carry lookahead adder (CLA) is proposed by using the modified all-N-transistor (ANT) design. The 32-bit CLA not only possesses few transistor count, but also occupies a small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 32-bit CLA can run up to 1.25 GHz at 3.3-V power supply. The output of the proposed CLA will be ready after 3.5 cycles. The proposed circuit is also easy to be expanded for long data additions. A physical chip is fabricated to verify the proposed circuit on silicon.

High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-/spl mu/m CMOS technology show that PDL with speed-enhanced skewed static (SSS) look reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.