32-bit Arithmetic Research Articles

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-constrained and battery-powered devices while retaining the flexibility granted by instruction processor-based architectures poses several challenges related to memory footprint, computational throughput, and energy efficiency. Low-bitwidth and mixed-precision arithmetic have been proven to be valid strategies for tackling these problems. We present Dustin, a fully programmable compute cluster integrating 16 RISC-V cores capable of 2-to 32-bit arithmetic and all possible mixed-precision combinations. In addition to a conventional Multiple-Instruction Multiple-Data (MIMD) processing paradigm, Dustin introduces a Vector Lockstep Execution Mode (VLEM) to minimize power consumption in highly data-parallel kernels. In VLEM, a single leader core fetches instructions and broadcasts them to the 15 follower cores. Clock gating Instruction Fetch (IF) stages and private caches of the follower cores leads to 38% power reduction. The cluster, implemented in 65 nm CMOS technology, achieves a peak performance of 58 GOPS and a peak efficiency of 1.15 TOPS/W.

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm

The energy efficiency of deep neural network (DNN) inference can be improved with custom accelerators. DNN inference accelerators often employ specialized hardware techniques to improve energy efficiency, but many of these techniques result in catastrophic accuracy loss on transformer-based DNNs, which have become ubiquitous for natural language processing (NLP) tasks. This article presents a DNN accelerator designed for efficient execution of transformers. The proposed accelerator implements per-vector scaled quantization (VSQ), which employs an independent scale factor for each 64-element vector to enable the use of 4-bit arithmetic with little accuracy loss and low energy overhead. Using a multilevel dataflow to maximize reuse, the 5-nm prototype achieves 95.6 tera-operations per second per Watt (TOPS/W) at 0.46 V on a 4-bit benchmarking layer with VSQ. At a nominal voltage of 0.67 V, the accelerator achieves 1734 inferences/s/W (38.7 TOPS/W) with only 0.7% accuracy loss on BERT-Base and 4714 inferences/s/W (38.6 TOPS/W) with 0.15% accuracy loss on ResNet-50 by using quantization-aware fine-tuning to recover accuracy, demonstrating a practical accelerator design for energy-efficient DNN inference.

TomocuPy - efficient GPU-based tomographic reconstruction with asynchronous data processing.

Fast 3D data analysis and steering of a tomographic experiment by changing environmental conditions or acquisition parameters require fast, close to real-time, 3D reconstruction of large data volumes. Here a performance-optimized TomocuPy package is presented as a GPU alternative to the commonly used central processing unit (CPU) based TomoPy package for tomographic reconstruction. TomocuPy utilizes modern hardware capabilities to organize a 3D asynchronous reconstruction involving parallel read/write operations with storage drives, CPU-GPU data transfers, and GPU computations. In the asynchronous reconstruction, all the operations are timely overlapped to almost fully hide all data management time. Since most cameras work with less than 16-bit digital output, the memory usage and processing speed are furthermore optimized by using 16-bit floating-point arithmetic. As a result, 3D reconstruction with TomocuPy became 20-30 times faster than its multi-threaded CPU equivalent. Full reconstruction (including read/write operations and methods initialization) of a 20483 tomographic volume takes less than 7 s on a single Nvidia Tesla A100 and PCIe 4.0 NVMe SSD, and scales almost linearly increasing the data size. To simplify operation at synchrotron beamlines, TomocuPy provides an easy-to-use command-line interface. Efficacy of the package was demonstrated during a tomographic experiment on gas-hydrate formation in porous samples, where a steering option was implemented as a lens-changing mechanism for zooming to regions of interest.

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits (ICs) fabrication industries. Because whenever device size comes down into narrow, designers facing many power density issues should be reduced by scaling threshold voltage and supply voltage. Initially, Complementary Metal Oxide Semiconductor (CMOS) technology supports power saving up to 32 nm gate length, but further scaling causes short severe channel effects such as threshold voltage swing, mobility degradation, and more leakage power (less than 32) at gate length. Hence, it directly affects the arithmetic logic unit (ALU), which suffers a significant power density of the scaled multi-core architecture. Therefore, it losses reliability features to get overheating and increased temperature. This paper presents a novel power minimization technique for active 4-bit ALU operations using Fin Field Effect Transistor (FinFET) at 22 nm technology. Based on this, a diode is directly connected to the load transistor, and it is active only at the saturation region as a function. Thereby, the access transistor can cutoff of the leakage current, and sleep transistors control the flow of leakage current corresponding to each instant ALU operation. The combination of transistors (access and sleep) reduces the leakage current from micro to nano-ampere. Further, the power minimization is achieved by connecting the number of transistors (6T and 10T) of the FinFET structure to ALU with 22 nm technology. For simulation concerns, a Tanner (T-Spice) with 22 nm technology implements the proposed design, which reduces threshold voltage swing, supply power, leakage current, gate length delay, etc. As a result, it is quite suitable for the ALU architecture of a high-speed multi-core processor.

Number-Theoretic Transform with Constant Time Computation for Embedded Post-Quantum Cryptography

Abstract In this article, we describe the principles and advantages of using the Number-Theoretic Transform (NTT) in post-quantum cryptography. We deal with usages of NTT in post-quantum algorithms included in the competition announced by the National Institute of Standards and Technology. Attention is paid to the fast multiplication of polynomials using NTT and negacyclic convolution. We also focus on the existing implementation of NTT and its modifications to analyze the effectiveness of individual modifications. Separate attention is paid to the Constant Time implementation of NTT because the constant computation time of the transformation decreases a possibility of side channel attack. We describe measurements performed on OS Linux Ubuntu 20.04 LTS environment in Linux kernel mode, with the highest attention to the measurement executed on a microcontroller with an ARM 32-bit core. Measurements performed on microcontroller units are done using 32-bit and 16-bit arithmetic to demonstrate how to achieve constant computation time of the transformation. We present the results and analysis of measurements performed using modified implementations.

Deep neural networks to correct sub-precision errors in CFD

Information loss in numerical physics simulations can arise from various sources when solving discretised partial differential equations. In particular, errors related to numerical precision (“sub-precision errors”) can accumulate in the quantities of interest when the simulations are performed using low-precision 16-bit floating-point arithmetic compared to an equivalent 64-bit simulation. On the other hand, low-precision computation is less resource intensive than high-precision computation. Several machine learning techniques proposed recently have been successful in correcting errors due to coarse spatial discretisation. In this work, we extend these techniques to improve CFD simulations performed with low numerical precision. We quantify the precision-related errors accumulated in a Kolmogorov forced turbulence test case. Subsequently, we employ a Convolutional Neural Network together with a fully differentiable numerical solver performing 16-bit arithmetic to learn a tightly-coupled ML-CFD hybrid solver.11The code and models developed in this work are available at https://github.com/akasharidas/subprecision-cfd. Compared to the 16-bit solver, we demonstrate the efficacy of the hybrid solver towards improving various metrics pertaining to the statistical and pointwise accuracy of the simulation.

4-BIT Arithmetic Logic Unit (ALU) using Full Swing GDI Technique

4-BIT Arithmetic Logic Unit (ALU) using Full Swing GDI Technique

Fluid Simulations Accelerated With 16 Bits: Approaching 4x Speedup on A64FX by Squeezing ShallowWaters.jl Into Float16.

Most Earth‐system simulations run on conventional central processing units in 64‐bit double precision floating‐point numbers Float64, although the need for high‐precision calculations in the presence of large uncertainties has been questioned. Fugaku, currently the world's fastest supercomputer, is based on A64FX microprocessors, which also support the 16‐bit low‐precision format Float16. We investigate the Float16 performance on A64FX with ShallowWaters.jl, the first fluid circulation model that runs entirely with 16‐bit arithmetic. The model implements techniques that address precision and dynamic range issues in 16 bits. The precision‐critical time integration is augmented to include compensated summation to minimize rounding errors. Such a compensated time integration is as precise but faster than mixed precision with 16 and 32‐bit floats. As subnormals are inefficiently supported on A64FX the very limited range available in Float16 is 6 × 10−5 to 65,504. We develop the analysis‐number format Sherlogs.jl to log the arithmetic results during the simulation. The equations in ShallowWaters.jl are then systematically rescaled to fit into Float16, using 97% of the available representable numbers. Consequently, we benchmark speedups of up to 3.8x on A64FX with Float16. Adding a compensated time integration, speedups reach up to 3.6x. Although ShallowWaters.jl is simplified compared to large Earth‐system models, it shares essential algorithms and therefore shows that 16‐bit calculations are indeed a competitive way to accelerate Earth‐system simulations on available hardware.

Rethinking Embedded Blocks for Machine Learning Applications

The underlying goal of FPGA architecture research is to devise flexible substrates that implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing, and image processing applications through high-precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: (1) higher computational density and (2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem formulation involving computing nested loops over multiply-accumulate (MAC) operations, which covers many basic linear algebra primitives and standard deep neural network (DNN) kernels. A quantitative methodology for deriving efficient coarse-grained compute block architectures from benchmarks is then proposed together with a family of new embedded blocks, called MLBlocks. An MLBlock instance includes several multiply-accumulate units connected via a flexible routing, where each configuration performs a few parallel dot-products in a systolic array fashion. This architecture is parameterized with support for different data movements, reuse, and precisions, utilizing a columnar arrangement that is compatible with existing FPGA architectures. On synthetic benchmarks, we demonstrate that for 8-bit arithmetic, MLBlocks offer 6× improved performance over the commercial Xilinx DSP48E2 architecture with smaller area and delay; and for time-multiplexed 16-bit arithmetic, achieves 2× higher performance per area with the same area and frequency. All source codes and data, along with documents to reproduce all the results in this article, are available at http://github.com/raminrasoulinezhad/MLBlocks .

Design of 64-Bit Arithmetic Logic Unit Using Improved Timing Characterization Methodology for RSFQ Cell Library

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

WITHDRAWN: Design of Robust Pole Configuration Controller Based on Embedded Network Distributed Single Input System

Abstract Robust control methods today are primarily solutions and the optimization process is presented as a set of optimization problems depends on the mathematical properties of the objective function. The proposed method, solving a polynomial equation based on the fixed characteristic polynomial is selected, including introducing a parameter solution having a known parameter structure of the controller.The embedded controller model should be modified to include an input / output interface with an external device. The method also includes a common reference function, which allows the possibility of different unrelated may consist of a standard, multi-objective optimization strict standard, mixed sensitivity problem applications, and other closed-loop constraints. Optimized design of the controller, clustering K- means the algorithm is executed.The following control performance parameters at different time and frequency domain studies, and is uncertain process parameters deviations thereof. Controller tuning rules are used for the process using a test bench, and it also the computational complexity analysis and process algorithms dynamics and sampled non- dominant pole type different types of distribution of data point's stable solution that provides an implementation of the hypothesis test for robustness. In the best case, these control law with single-precision (32-bit) arithmetic is implemented in the embedded processor.

Number Formats, Error Mitigation, and Scope for 16-Bit Arithmetics in Weather and Climate Modeling Analyzed With a Shallow Water Model.

The need for high‐precision calculations with 64‐bit or 32‐bit floating‐point arithmetic for weather and climate models is questioned. Lower‐precision numbers can accelerate simulations and are increasingly supported by modern computing hardware. This paper investigates the potential of 16‐bit arithmetic when applied within a shallow water model that serves as a medium complexity weather or climate application. There are several 16‐bit number formats that can potentially be used (IEEE half precision, BFloat16, posits, integer, and fixed‐point). It is evident that a simple change to 16‐bit arithmetic will not be possible for complex weather and climate applications as it will degrade model results by intolerable rounding errors that cause a stalling of model dynamics or model instabilities. However, if the posit number format is used as an alternative to the standard floating‐point numbers, the model degradation can be significantly reduced. Furthermore, mitigation methods, such as rescaling, reordering, and mixed precision, are available to make model simulations resilient against a precision reduction. If mitigation methods are applied, 16‐bit floating‐point arithmetic can be used successfully within the shallow water model. The results show the potential of 16‐bit formats for at least parts of complex weather and climate models where rounding errors would be entirely masked by initial condition, model, or discretization error.

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems

Deep neural networks (DNNs) are increasing their presence in a wide range of applications, and their computationally intensive and memory-demanding nature poses challenges, especially for embedded systems. Pruning techniques turn DNN models into sparse by setting most weights to zero, offering optimization opportunities if specific support is included. We propose a novel pipelined architecture for DNNs that avoids all useless operations during the inference process. It has been implemented in a field-programmable gate array (FPGA), and the performance, energy efficiency, and area have been characterized. Exploiting sparsity yields remarkable speedups but also produces area overheads. We have evaluated this tradeoff in order to identify in which scenarios it is better to use that area to exploit sparsity, or to include more computational resources in a conventional DNN architecture. We have also explored different arithmetic bitwidths. Our sparse architecture is clearly superior on 32-bit arithmetic or highly sparse networks. However, on 8-bit arithmetic or networks with low sparsity it is more profitable to deploy a dense architecture with more arithmetic resources than including support for sparsity. We consider that FPGAs are the natural target for DNN sparse accelerators since they can be loaded at run-time with the best-fitting accelerator.

Ballistic Transport in High-Performance and Low-Power Sub-5 nm Two-Dimensional ZrNBr MOSFETs

Here, the electronic properties and ballistic transport properties of two-dimensional (2D) ZrNBr are comprehensively investigated by the nonequilibrium Green’s function coupled with density functional theory. 2D ZrNBr has a wide direct band gap of 1.82 eV with the highest mobility of 8700cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ . Both the n- and p-type 2D ZrNBr MOSFETs with 5-nm channel length hold the on-currents above $2300~\mu \text{A}/\mu \text{m}$ for high-performance devices and an on/off ratio exceeding 106 for low-power applications, which is of great value for the design of complementary circuits in 2D electronics. In addition, the energy-delay products of the single 2D ZrNBr MOSFETs and the 32-bit Arithmetic Logic Unit show more potential compared to other 2D materials and CMOS proposals. Thus, this work broadens a promising path towards beyond-silicon electronic systems.

Magnetic Logic Gate Based on Polarized Spin Waves

Spin wave, the precession of magnetic order in magnetic materials, is a collective excitation that carries spin angular momentum. Similar to the acoustic or optical waves, the spin wave also possesses the polarization degree of freedom. Although such polarization degrees of freedom are frozen in ferromagnets, they are fully unlocked in antiferromagnets or ferrimagnets. Here we introduce the concept of magnetic gating and demonstrate a spin wave analog of the Datta-Das spin transistor in antiferromagnet. Utilizing the interplay between polarized spin wave and the antiferromagnetic domain walls, we propose a universal logic gate of pure magnetic nature, which realizes all Boolean operations in one single magnetic structure. We further construct a full functional 4-bit Arithmetic Logic Unit using only sixteen spin wave universal logic gates, operating in a weaving fashion as a Jacquard loom machine. The spin wave-based architecture proposed here also sets a model for the future energy efficient non-volatile computing, the distributed processing-in-memory computing, and the evolvable neuromorphic computing.

Design and Analysis of an Arithmetic and Logic Unit using Single Electron Transistor

The demand for low power dissipation and increasing speed elicits numerous research efforts in the field of nano CMOS technology. The Arithmetic Logic Unit is the core of any central processing unit. In this paper, we designed a 4-bit Arithmetic and Logic Unit (ALU) using Single Electron Transistor (SET). Single-electron transistor (SET) is a new type of switching nanodevice that uses controlled single-electron tunneling to amplify the current. The single-electron transistor (SET) is highly scalable and possesses ultra-low power consumption when compared to conventional semiconductor devices. Reversible logic gates designed using SET are used for performing 4-bit arithmetic operations. We modelled symmetric single gate SET operating at room temperature using Verilog A code. The design is carried out in cadence simulation environment. The 4-bit SET based ALU design exhibits the power of 0.52 nW and delay of 350pS.

Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors

A 16-bit bit-slice arithmetic logic unit (ALU) is proposed for 32-/64-bit rapid single-flux-quantum microprocessors. It is based on a Ladner-Fischer adder. The ALU covers all of the ALU operations for MIPS32 instructions set. And each of the two 64-bit operands is divided into four slices of 16 bits each. The ALU uses synchronous concurrent-flow clocking and consists of 11 pipeline stages. The proposed ALU can be used for any 16n-bit processing.

Fast approximations of exponential and logarithm functions combined with efficient storage/retrieval for combustion kinetics calculations

We developed two approaches to speed up combustion chemistry simulations by reducing the amount of time spent computing exponentials, logarithms, and complex temperature-dependent kinetics functions that heavily rely on them. The evaluation of these functions is very accurate in 64-bit arithmetic, but also slow. Since these functions span several orders of magnitude in temperature space, some of this accuracy can be traded with greater solution speed, provided that the governing ordinary differential equation (ODE) solver still grants user-defined solution convergence properties. The first approach tackled the exp() and log() functions, and replaced them with fast approximations which perform bit and integer operations on the exponential-based IEEE-754 floating point number machine representation. The second approach addresses complex temperature-dependent kinetics functions via storage/retrieval. We developed a function-independent piecewise polynomial approximation method with the following features: it minimizes table storage requirements, it is not subject to ill-conditioning over the whole variable range, it is of arbitrarily high order n > 0, and is fully vectorized. Formulations for both approaches are presented; and their performance assessed against zero-dimensional reactor simulations of hydrocarbon fuel ignition delay, with reaction mechanisms ranging from 10 to 104 species. The results show that, when used concurrently, both methods allow global speed-ups of about one order of magnitude even with an already highly-optimized sparse analytical Jacobian solver. The methods also demonstrate that global error is within the integrator’s requested accuracy, and that the solver’s performance is slightly positively affected, i.e., a slight reduction in the number of timesteps per integration is seen.

Low power sub‐threshold asynchronous quasi‐delay‐insensitive 32‐bit arithmetic and logic unit based on autonomous signal‐validity half‐buffer

The authors propose an asynchronous-logic (async) quasi-delay-insensitive (QDI) autonomous signal-validity half-buffer (ASVHB) realisation approach for low power sub-threshold operation (V DD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used exclusively to simplify the circuit implementation for QDI protocol. Second, the ASVHB realisation approach applies the fine-grained gate-level method, which propagates data through a single-cell datapath pipeline to maximise the throughput rate. Third, the ASVHB realisation approach adopts the static-logic implementation, which maintain stable output states (by connecting them directly to the power rails), to feature high robustness for sub-threshold operation. They compare their ASVHB realisation approach against the competitive reported weak-conditioned half-buffer (WCHB) and pre-charged half-buffer (PCHB) realisation approaches. The WCHB and PCHB library cells, on average, require ∼2.1 × and ∼1.9 × more transistors than the ASVHB library cells. With respect to a 3-stage pipeline realisation, the WCHB and PCHB pipelines, on average, require 1.8 × and 1.5× more transitions per-cycle than the ASVHB pipeline. They design an async 32-bit arithmetic and logic unit (ALU) based on the proposed ASVHB realisation approach (at 65 nm CMOS process). Their ASVHB ALU occupies 0.092 mm2, and in many merits, outperforms the WCHB and PCHB counterparts. The WCHB and PCHB counterparts require ∼1.7 × and ∼1.4× more transistors, respectively, than their design. At the sub-threshold voltage of V DD = 0.2 V, the WCHB and PCHB counterparts dissipate ∼1.7× and ∼2.6× more energy, respectively, and are, respectively, ∼0.95× and ∼0.73× slower throughput.