28nm UTBB FD-SOI Research Articles

Common source power amplifier design for 5G application in 28-nm UTBB FD-SOI technology

The telecommunication market examines a highly growing demand for RF mobile devices where low latency and high performance are ongoing improvement. The power amplifier (PA) is a major element of the radio frequency front-end; especially if power consumption and bandwidth are considered. This paper presents the design of 5G mm-wave PA using both Common Source Class-AB and Class-J topologies utilizing 28-nm UTBB FD-SOI technology and its body bias technique. Upon taking into consideration the parasitic extraction of the transistor, RF pads, and interconnection to ground, a comparison is made and the theoretical effectiveness of Class-J topology for single stage large signal amplification is simulated. Moreover, two distinct transistors - widths of 250 µm and 350 µm - are simulated where each has its own topology in order to study the impact of increasing the width on the performance of the PA. The stability of the designed Power Amplifiers is taken into consideration and the unconditional stability conditions are approved. While 5G spectral band is not yet specified and determined, recent studies proved that the 28 GHz band is particularly effective for 5G mobile standardization.

A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35–1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables bit-interleaving. The proposed assist scheme can be combined with conventional assist schemes to further lower minimum write operational voltage of the SRAM by 70–130 mV at iso-performance without causing reliability concerns. A 32 kb instance is fabricated in 28-nm UTBB-FDSOI technology and efficiency of the proposed scheme is demonstrated with lowest write voltage of 0.32 V. Multiple read assist schemes have been used to simultaneously lower read voltage to 0.35 V. 50 MHz operation is measured when integrated in a DSP processor at 0.358 V. Low voltage and wide voltage range figure of merits are also defined to benchmark the proposed solutions with other works.

Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology

This paper presents an in-depth analysis of the impact of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI technology. Three types of short defects are considered for our investigation, namely resistive short to ground terminal, resistive short to power supply terminal (VDD), and intergate resistive bridging defect. The two implementation options offered by the technology, i.e., low VT (LVT) and regular VT (RVT) devices are also studied. Defect detectability is evaluated in the context of logic test using the concept of critical resistance. The optimal body-biasing, supply voltage, and temperature settings to achieve the maximum defect coverage are determined through HSPICE simulations using a didactic circuit implemented with 28-nm UTBB FDSOI gate library. An analytical analysis is also proposed based on the on-resistance model of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. In addition, this paper quantifies the individual as well as the combined improvements in detection brought by body-biasing, supply voltage, and temperature settings for the different defect types and different implementations.

Two mm-Wave VCOs in 28-nm UTBB FD-SOI CMOS

Two 60-GHz band voltage controlled oscillators (VCOs) designed in a 28-nm ultrathin body and buried oxide fully depleted silicon on insulator (UTBB FD-SOI) CMOS process are demonstrated and compared. Both VCOs have identical cross-coupled nMOS cores and dissipate 3.15 mW from a 0.9-V supply. The first design uses a standard FET current source and achieves a figure of merit (FOM) of −181 dBc/Hz, whereas the second employs a filtered current source and achieves a state-of-the-art FOM of −187 dBc/Hz. The achieved 6-dB improvement demonstrates the efficiency of the filtering technique at millimeter wave frequencies and the feasibility of efficient low-phase noise designs in 28-nm UTBB FD-SOI CMOS. The active area of the filtered VCO is $90\,\,\mu \text{m}\,\,\times 180\,\,\mu \text{m}$ and the standard VCO has an area of $80\,\,\mu \text{m}\,\,\times 110\,\,\mu \text{m}$ .

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI.

This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 µm by 250 µm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II

This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology

The need for a novel multi-scale ESD (ElectroStatic Discharge) network recognition and verification methodology is described in this paper. The proposed solution is used to limit the risk of ESD design errors and to enhance IC reliability, independently of the implemented ESD protection strategy and the type of package assembly technique. This method relies on a topology-aware & graph-based verification paradigm which is generic enough to be usable at every step of the design flow. Its efficiency is illustrated with examples involving custom I/O ring portions in 28nm UTBB FD-SOI High-K metal gate technology.

Performance vs. reliability adaptive body bias scheme in 28 nm & 14 nm UTBB FDSOI nodes

This paper shows the advantages of using body bias. Experiments are performed in 14nm and 28nm UTBB FDSOI transistors and ring oscillators (ROs). The impact of body bias on performance and reliability is highlighted. The body biasing offers significant advantages for adapting the tradeoff between reliability and performance in logic circuits without changing the design margins. With FDSOI technology, we have an additional degree of freedom of process variability compensation by using body bias voltage (Adaptive Body Bias, ABB) next to supply voltage compensation used before. We show that ABB compensation technique presents better results for a complete power optimization.

An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI

A multistage continuous-time linear equalizer (CTLE) design with a controllable transfer function is presented. The entire frequency range of interest, from dc to gain roll-off frequency, is divided into six regions, and the transfer function in each region is independently matched to be the inverse of the channel transfer function. The equalizer is used for 6-Gb/s data transfer per channel for high-definition multimedia interface (HDMI) 2.0 receiver and 5.4-Gb/s data transfer per channel for DisplayPort (DP) receiver designs. Fabricated in a 28-nm ultrathin body and buried oxide fully depleted silicon-on-insulator technology, the 0.06-mm2 CTLE consumes 30 mW to achieve up to 28-dB peaking. The entire receiver channel occupies 0.21 mm2, consumes 55 mW, and achieves a power efficiency of 9.2 pJ/bit at 6 Gb/s. This design achieves a jitter tolerance of 0.7 unit interval (UI) up to 10 MHz for HDMI and 0.42 UI up to 100 MHz for DP, which is better than their respective specifications.

Body Bias usage in UTBB FDSOI designs: A parametric exploration approach

Some years ago, UTBB FDSOI has appeared in the horizon of low-power circuit designers. With the 14nm and 10nm nodes in the road-map, the industrialized 28nm platform promises highly efficient designs with Ultra-Wide Voltage Range (UWVR) thanks to extended Body Bias properties. From the power management perspective, this new opportunity is considered as a new degree of freedom in addition to the classic Dynamic Voltage Scaling (DVS), increasing the complexity of the power optimization problem at design time. However, so far no formal or empiric tool allows to early evaluate the real need for a Dynamic Body Bias (DBB) mechanism on future designs. This paper presents a parametric exploration approach that analyzes the benefits of using Body Bias in 28nm UTBB FDSOI circuits. The exploration is based on electrical simulations of a ring-oscillator structure. These experiences show that a Body Bias strategy is not always required but, they underline the large power reduction that can be achieved when mandatory. Results are summarized in order to help designers to analyze how to choose the best dynamic power management strategy for a given set of operating conditions in terms of temperature, circuit activity and process choice. This exploration contributes to the identification of conditions that make DBB more efficient than DVS, and vice versa, and when both methods are mandatory to optimize power consumption.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44V to 1.2V. In addition, the architecture allows a wide range of body bias to be applied from −1.8V to 0.9V. The peak energy efficiency 60 GOPS/W is achieved at 0.5V supply voltage and 0.5V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2V of body biasing, and compensate temperature variation in the range −40°C to 120°C exploiting −1.1V to 0.8V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

Dual Ground Plane for high-voltage MOSFET in UTBB FDSOI technology

For the first time, the investigation and fabrication of a high-voltage MOSFET (HVMOS) in Ultra-Thin Body and Buried oxide Fully Depleted technology (UTBB-FDSOI) is reported. Through TCAD simulations, the lateral electric field profile and related breakdown voltage behaviour are studied. Taking benefit of the FDSOI assets, an original HVMOS architecture, featuring a Dual Ground Plane, is proposed to optimize the electric field profile distribution. As a new lever for high voltage, the Dual Ground Plane enables a “RESURF-like” effect, electrostatically improving classical HVMOS figures of merit: the breakdown voltage (BV) and the specific-on resistance (RON.S). Experimental results confirm the potential of the Dual Ground Plane solution for HVMOS device in 28nm UTBB-FDSOI technology and beyond.