28nm FDSOI Research Articles

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA

Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT) domain require complex on-device signal analysis and data reduction to maximize energy efficiency on these energy-constrained devices. Coarse-grained reconfigurable architectures (CGRAs) have been proposed as a good compromise between flexibility and energy efficiency for ultra-low power (ULP) signal processing. Existing CGRAs are often specialized and domain-specific or can only accelerate simple kernels, which makes accelerating complete applications on a CGRA while maintaining high energy efficiency an open issue. Moreover, the lack of instruction set architecture (ISA) standardization across CGRAs makes code generation using current compiler technology a major challenge. This work introduces R-Blocks; a ULP CGRA with HW/SW co-design tool-flow based on the OpenASIP toolset. This CGRA is extremely flexible due to its well-established VLIW-SIMD execution model and support for flexible SIMD-processing, while maintaining an extremely high energy efficiency using software bypassing, optimized instruction delivery, and local scratchpad memories. R-Blocks is synthesized in a commercial 22-nm FD-SOI technology and achieves a full-system energy efficiency of 115 MOPS/mW on a common FFT benchmark, 1.45× higher than a highly tuned embedded RISC-V processor. Comparable energy efficiency is obtained on multiple complex workloads, making R-Blocks a promising acceleration target for general-purpose computing.

A 28GHz, Switched-Cascode, Class E Amplifier in 22nm CMOS FDSOI Technology

A 28GHz, Switched-Cascode, Class E Amplifier in 22nm CMOS FDSOI Technology

A reconfigurable RF front-end for 5G direct sampling receivers with an optimized calibration scheme

This paper presents a reconfigurable radio frequency front-end (RFFE) tailored for direct RF sampling receivers operating within Frequency Range 1 (FR-1) of the 5G spectrum. It consists of a balun-LNA, a noise-cancelling, current-reuse, Q-enhanced filter, and a programmable gain amplifier (PGA). Fabricated in 22-nm FD-SOI technology, the RFFE covers the entire frequency range from 1.7 to 6.4 GHz with a tunable bandwidth ranging from 50 MHz to 1.2 GHz. The experimental results confirm that the RFFE achieves 3.9 dB NF, 55 dB ultimate OOB rejection, −4 dBm IB-IIP3, and 23 dBm OOB-IIP3. Furthermore, a digital calibration scheme is proposed to compensate for process, voltage, and temperature (PVT) variations, achieving lower than 2 % error in 6.61 µs on average. Subsequently, a proximal policy optimization (PPO) agent is employed to choose the optimal policy for the successive adjustments of quality factors and resonance frequencies of the filter’s resonators. As a result, the proposed reinforcement learning algorithm reduces the calibration’s convergence time by 59 %.

A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI

A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI

A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI

A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI

Analysis and Design of a Dual-Core $D$-Band Colpitts Oscillator With 150-GHz Third-Harmonic Extraction in 22-nm CMOS FD-SOI

Analysis and Design of a Dual-Core $D$-Band Colpitts Oscillator With 150-GHz Third-Harmonic Extraction in 22-nm CMOS FD-SOI

Strain mapping and simulation of transistor structures in a 22nm FDSOI technology

Strain mapping and simulation of transistor structures in a 22nm FDSOI technology

Investigation of p- and n-Type Quantum Dot Arrays Manufactured in 22nm FDSOI CMOS at 2-4 K and 300 K

Investigation of <i>p</i>- and <i>n</i>-Type Quantum Dot Arrays Manufactured in 22nm FDSOI CMOS at 2-4 K and 300 K

Analytical Modeling of Cryogenic Subthreshold Currents in 22-nm FDSOI Technology

Analytical Modeling of Cryogenic Subthreshold Currents in 22-nm FDSOI Technology

The future is frozen: cryogenic CMOS for high-performance computing

Low Temperature CMOS or Cryogenic CMOS is a promising avenue for continuation of Moore’s Law while serving high performance computing (HPC) needs. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With optimal threshold voltage engineering, the device ON current can be enhanced further, translating to higher performance. In this article, we use experimentally calibrated data to tune the threshold voltage and investigate the power performance area (PPA) of cryogenic CMOS at device, circuit and system level. We also present results from measurement and analysis of functional memory chips fabricated in 28nm bulk CMOS and 22nm FDSOI operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems will be discussed.

Characterization of LDO Induced Increment of SEE Sensitivity for 22-nm FDSOI SRAM

Characterization of LDO Induced Increment of SEE Sensitivity for 22-nm FDSOI SRAM

A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking

A new design methodology for reducing the area and power of standard cell ASICs that uses a combination of differential flipflops and a method of deliberate clock-skewing, called local clocking (LC), is described. LC introduces clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of a new differential flipflop, referred to as KVFF, that is functionally identical to a master-slave edgetriggered D flipflop, but in addition, produces a completion signal that is a skewed version of its input clock, which is used to clock other flipflops; and (2) an efficient algorithm that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. These are reduced because deliberate skew introduces extra slack on the logic cones that feed the target flipflops, which is exploited by synthesis tools to reduce area and power. Furthermore, the area and power overhead of conventional methods of introducing skew, e.g. buffers, is eliminated. Local clocking is shown to result in significant improvements in area, power and wirelength for several, publicly available, benchmark circuits for 65nm bulk CMOS and 28nm FDSOI technologies. For 65nm, the average improvement in area, power and wirelength were 27.7%, 13.4%, and 21.0%, respectively. For 28nm FDSOI the average improvement in area, power, and wirelength were 20.0%, 10.5%, and 30.5%, respectively. In addition, the paper demonstrates how local clocking can be used to eliminate hold time violations.

Impact of High Temperature Up to 175 °C on the DC and RF Performances of 22-nm FD-SOI MOSFETs

Impact of High Temperature Up to 175 °C on the DC and RF Performances of 22-nm FD-SOI MOSFETs

Impact of CnRx Structure on Soft Error Rates of Flip-Flop Designs at 22-nm FD SOI Node

Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single cell design. In this paper the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates of stacked-transistor flip-flops are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high performance and radiation tolerant cells using the CnRx construct.

On noise-induced transient bit flips in subthreshold SRAM

We propose a rigorous SPICE simulation framework, compatible with industrial process design kits, to observe transient bit flips in CMOS SRAM due to the intrinsic transistor noise. The parameters of transient noise simulation are selected according to the noise behaviour and bandwidth of the inverter, however under CPU-time constraint. The methodology is illustrated in 28nm FD-SOI technology. We study the combined effects of the random telegraph noise, flicker and thermal noise sources, for the first time to our knowledge. The extracted mean times to failure (MTTF) are compared to those reported in the literature in extreme voltage, temperature and variability conditions. The MTTF spans from below 0.1ms to 108s, following a theoretical trend logMTTF∝VDD2.

A High-Performance, Low Power Research Hearing Aid featuring a High-Level Programmable Custom 22nm FDSOI SoC.

With advances in algorithmic hearing aid research, the need for high-level programmable, behind-the-ear (BTE) wearable and low-power research platforms is emerging. These can be used to test new algorithms in real-world scenarios. Although various groups are developing different portable solutions, they are not in a BTE form factor. For this reason, the devices must be worn around the neck or somewhere on the body, which causes limited mobility and can lead to inaccurate research results. Therefore, this work presents a fully integrated and functional hearing aid research platform that weighs only 5 grams and can be worn behind the ear. The platform is high-level programmable, features wireless technologies such as near-field magnetic induction (NFMI) and Bluetooth Low Energy (BLE), and integrates two micro-electro-mechanical systems (MEMS) microphones and an external speaker. The audio processor of the system is based on a new custom, low-power 22nm mixed-signal system on chip (SoC). Different real-world use cases, like a dynamic compressor, are used to evaluate the platform. With a total power consumption of 47 mW, the rechargeable device achieves a run-time of six hours. When the wireless interfaces are turned off, the power consumption drops to 31 mW, and the run-time increases to nine hours.Clinical relevance-The proposed research hearing aid demonstration platform can be used portable and outside the clinical setting for algorithmic research. With its behind-the-ear form factor and rechargeable battery, studies can be conducted for several hours without restricting patient movement in real-world scenarios.

UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI

Sensitivity to process, voltage, and temperature (PVT) variations constitutes a serious obstacle in ultralow-voltage/ultralow-power (ULV/ULP) circuits and systems. To address this challenge, we propose a unified frequency/back-bias regulation (UFBBR) macro embedded in a custom ULP ARM Cortex-M4 microcontroller unit (MCU) manufactured in 28-nm FDSOI technology. The UFBBR technique combines the generation of a 32-to-80 MHz system clock and asymmetric adaptive back biasing for PVT compensation. Relying on a novel dual-output frequency-locked loop, it senses both the logic speed and the N/PMOS process imbalance using back-bias-controlled oscillators, and generates adequate forward back-bias voltages with digitally-controlled oscillators followed by switched-capacitor charge-pumps for fast current actuation. Compared to a situation with zero back biasing and appropriate frequency/voltage margins, the UFBBR provides 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> of frequency boosting at 0.4 V or 180 mV of voltage reduction at 64 MHz. It leverages software-programmable configuration knobs to achieve a fast wake-up of 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\upmu$</tex-math> </inline-formula> s and an in-lock power of 22 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\upmu$</tex-math> </inline-formula> W, with an area overhead below 0.032 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In sleep, it drives the back-bias voltages towards 0 V and disables the clock for minimum power consumption. These features help the MCU system achieve a minimum energy point of 5.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\upmu$</tex-math> </inline-formula> W/MHz and a sleep power of 7.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\upmu$</tex-math> </inline-formula> W.

SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node

Compared with bulk technologies, Fully-depleted silicon-on-insulator (FD SOI) technology nodes show better resistance to single-event upsets. However, additional hardening techniques should be investigated to mitigate upsets at this technology node. Single-event (SE) performance of multiple hardened flip-flop (FF) designs based on Schmitt-trigger circuits along with a conventional DFF design in a 22-nm FD SOI process is presented. FF designs were tested using alpha particles and heavy-ions. Results show significant reductions in SEU cross-sections compared with the conventional design. Alpha particle exposures showed zero upsets for all FF designs tested. Schmitt-trigger-based FF designs showed from 2× to 200× improvement in heavy-ion SEU cross-sections compared with the conventional DFF design.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition.

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 , and an input-referred noise of 7.7 ± 0.4 in the AP band and 11.9 ± 1.1 in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications

This brief presents a 2-stage, low-power, millimeter-wave (mm-wave) LNA that aims at first to reduce its passive area through a transformer formed with inductors between the gate and source sides of the input transistor in a source-degenerated cascode. While reducing the passive area, the introduced transformer creates a magnetic feedback that further reduces the LNA’s noise figure (NF). We provide a theoretical analysis of this feedback-based noise reduction method and validate it with simulations and experimental results. The LNA has been fabricated in 22-nm FD-SOI CMOS and has a core area of only 0.09 mm2. The measurement results show that this design achieves a minimum 2.1 dB NF and a maximum 23.1 dB gain between 23.7–28.5 GHz at a power dissipation of only 5.6 mW from a 0.6V supply. Furthermore, despite using only a 0.6V supply voltage, IIP3 can still reach −16.5 dBm at 28 GHz. Targeting mm-wave 5G applications, the presented LNA is among the best-in-class with a sub-1V supply voltage.