14nm Tri-gate CMOS Research Articles

Analysis of Neutron-Induced Multibit-Upset Clusters in a 14-nm Flip-Flop Array

We report a detailed analysis of neutron-induced multibit-upset (MBU) clusters measured from flip-flop arrays implemented in a 14-nm trigate CMOS. Depending on the strike location, charge collection efficiency, and circuit topology, the MBU clusters are characterized in terms of size and span, and a qualitative first-order analysis has been presented. A novel MBU analysis framework has been demonstrated that uses a weighted sliding window to characterize MBU clusters efficiently and accurately with minimal double-counting or mischaracterization of cluster size. To further explain the relative MBU cross sections, the unique MBU patterns extracted from measured data have been studied and analyzed to find layout dependencies. The results show the strong correlation between the internode proximity and MBUs. The analysis shows a higher soft error rate (SER) cross section for smaller MBU cluster size and smaller span while the bigger clusters have lower contribution toward overall MBU SER.

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

This paper describes a unified static/dynamic entropy generator based on a 512-b common entropy source (ES) array fabricated in 14-nm tri-gate CMOS with reconfigurable and adaptive post-processing circuits implemented on Arria 10 FPGA, targeted for flexible and secure privacy preserving mutual authentication on compact trusted mote platforms at the edge of internet of things. Several conditioning techniques that include temporal majority voting (TMV)-assisted ES array segregation with integrated bias tracking, three-way in-line self-calibration for tolerance to process–voltage–temperature variation, tri-level hierarchical Von Neumann (VN) extraction to maximize entropy harvesting, soft-dark bit masking for improving physically unclonable function (PUF) stability, and selective stress hardening to co-optimize the ES array for static-dynamic entropy with bias aware device aging enable simultaneous PUF and true random number generator (TRNG) operation with 1.48 and 0.56 Gb/s throughput, respectively, measured at 650 mV, 70 °C. The all-digital design with a compact layout footprint of 2114 $\mu \text{m}^{2}$ facilitates seamless integration in area constrained system-on-chips while achieving: 1) 25% area savings over conventional separate PUF and TRNG implementations; 2) cryptographic quality TRNG stream that passes all NIST randomness tests with 0.38 average p-value; 3) $1.6\times $ higher extractor performance at $9\times $ lower area with 750-gate hierarchical VN circuit over conventional light-weight entropy extractors; 4) 0.9996/0.99997 static/dynamic Shannon entropy indicating unbiased PUF/TRNG streams; 5) ultra-low energy consumption of 2.5 and 0.46 pJ/bit measured at 650 mV, 70 °C in TRNG and PUF modes; 6) 40% higher TRNG throughput with three-way self-calibration featuring coarse-grain column swap, fine-grain incremental ES substitution, and residual entropy recycling; 7) resistance to power injection attacks as measured by 64% higher performance over un-calibrated design in the presence 200-mV supply noise; 8) 2.8% PUF bit-error measured at 0.55–0.75 V, 25 °C–110 °C with 15-way TMV and soft dark-bit masking over a window of 100 cycles; 9) $14.8\times $ inter and intra-PUF hamming distance separation; and 10) 56% reduction in discarded ES cells with selective stress hardening to opportunistically reinforce/nullify pre-existing bias in PUF/TRNG candidate cells. To our knowledge, this is the first reported unified PUF-TRNG implementation enabling simultaneous generation of high-entropy chip-ID and encryption keys in real time.

A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS

A fully integrated digitally controlled buck voltage regulator, featuring hysteretic and pulse frequency modulation control for maximum light load efficiency, with 3-D through-silicon-via-based on-die solenoid inductor with a planar magnetic core in 14-nm tri-gate CMOS, demonstrates 111 nH/mm2 inductance density and 80% conversion efficiency. The inductance density demonstrated is 20 $\times $ higher than comparable on-die lateral- or spiral-based inductor densities leading to higher light load efficiency.

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS

A fully integrated digitally controlled two-phase buck voltage regulator (VR) with on-die solenoid inductors with a planar magnetic core is demonstrated in 14-nm tri-gate CMOS for fine-grained power delivery/management domains of high power density in system-on-chips while enabling ultra-thin (z-height) packages. The VR achieves 1-A/mm2 power density for 400-mA load current with a measured peak efficiency of 84% at 100-MHz switching frequency including a digital PWM with >9 bits (8 ps) of resolution.

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in ~5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying $1.84~\mu \text{m}^{2}$ achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70 °C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55–0.75 V, and 25 °C–110 °C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid clock routing measured from 49.5% hamming distance between array’s evaluation and wake-up states.

3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication

A configurable, channel-adaptive K-best MIMO detector for multi-mode wireless communications that adapts computation to varying channel conditions to achieve high energy-efficiency is presented. An 8-stage configurable MIMO detector supporting up to a 4×4 MIMO array and BPSK to 16-QAM modulation schemes has been implemented and simulated in 0.80V, 22nm Tri-gate CMOS process. Dynamic clock gating and power gating enable on-the-fly configuration and adaptive tuning of search radius K to channel response which results in 10% to 51% energy-efficiency improvement over non-adaptive K-best MIMO detectors. During unfavorable channel conditions, the MIMO detector satisfies target BER by setting K=5. For favorable channel conditions, K is reduced to 1, where 22nm circuit simulations show 68% energy reduction. At 1.0GHz target frequency, the total power consumption is 15mW (K=1) to 35mW (K=5), resulting in energy-efficiency of 14.2pJ/bit (K=1) to 44.7pJ/bit (K=5) and 3.2Gbps throughput.

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budget from communication toward computation. As core counts scale into the 100s, on-chip interconnect fabrics must support increasing heterogeneity and voltage/clock domains. Synchronous NoCs require either a single clock distributed globally or clock-crossing data FIFOs between clock domains [1]. A global clock requires costly full-chip margining and significant power and area for clock distribution, while synchronizing data FIFOs add power, performance, and area overhead per clock crossing. Source-synchronous NoCs mitigate these penalties by forwarding a local clock along with each packet, but still suffer from high data storage power due to packet switching. Circuit switching removes intra-route data storage, but suffers from low network utilization due to serialized channel setup and data transfer [2]. Hybrid packet/circuit switching parallelizes these operations for higher network utilization. A 16×16 mesh, 112b data, 256 voltage/clock domain NoC with source-synchronous operation, hybrid packet/circuit-switched flow control, and ultra-low-voltage optimizations is fabricated in 22nm tri-gate CMOS [3] to enable: i) 20.2Tb/s total throughput at 0.9V, 25°C, ii) a 2.7× increase in bisection bandwidth to 2.8Tb/s and 93% reduction in circuit-switched latency at 407ps/hop through source-synchronous operation, iii) a 62% latency improvement and 55% increase in energy efficiency to 7.0Tb/s/W through circuit switching, iv) a peak energy efficiency of 18.3Tb/s/W for near-threshold operation at 430mV, 25°C, and v) ultra-low-voltage operation down to 340mV with router power scaling to 363μW.