Factories and industrial warehouses are environments in which accidents can be easily produced. People on foot work in the same place where heavy machinery is operating. Therefore, when accidents occur, they frequently have severe consequences. To reduce the number of accidents and their effects, there are strict regulations on the workplace and workers participate in regular training activities. In recent years, there has been a great evolution in Advanced Driver Assistance Systems (ADAS) specially in public road vehicles. With the proper design, these systems may also help to improve safety in industrial environments. For example, an ADAS may warn industrial drivers about nearby pedestrians. Nevertheless, the development of ADAS in this context is complex because industrial environments and their machines are very heterogeneous. Hence, this paper describes a testbed developed to assess the design of ADAS for industrial vehicles. The testbed includes all the elements needed to evaluate an industrial ADAS: hardware, an event management system, a simulator of a warehouse and, an evaluation methodology. To determine the effectiveness of the testbed, the assessment of an ADAS designed to warn industrial drivers about nearby obstacles has also been performed. The assessment includes a subjective evaluation of the testbed and of the cognitive load generated during the evaluation. The results of this assessment are very promising. They show that the testbed is realistic and that it is effective for ADAS designers to analyse the reactions of drivers to the signals produced by the assistance systems under evaluation.

It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, "there's plenty of room at the top". The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF6/O2 is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF6/O2 plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules.

Cellular-connected Unmanned Aerial Vehicles (UAVs) require reliable wireless connections and will benefit from ultra-reliable and low-latency communication (URLLC) in 5G and beyond networks. 5G campus solutions, when integrating with Time-Sensitive Networking (TSN), can provide extended coverage and deterministic behavior for wireless links. However, one of the challenges for research in this direction is reliable yet cost-effective and flexible evaluation, which applies to academia and industry. We believe that open-source testbeds can effectively address the challenge due to their maturity and transparency in verifying evaluation results. Subsequently, we systematically survey and categorize testbeds in the literature that use commercial-off-the-shelf hardware. Our study outlines options for building a full-fledged testbed for integrating TSN with 5G and beyond for research and development. This study initiates one of the first steps toward facilitating future research toward practical deployment of TSN-5G integration.

For the 3 nm technology node, horizontal gate-all-around nanosheet devices offer a non-disruptive process transition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3 nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both $V_{\min}$ and read delay even at smaller cell areas.