This paper describes design requirements for VHDL-RF/MW/sup TM/. The resulting language design addresses distributed and full-wave interconnect models, frequency-domain modeling and parasitic interactions so as to maintain full conceptual and representational compatibility with VHDL, VHDL-AMS, Verilog, Verilog-AMS and SPICE.

Testing the adherence of a hardware description language (HDL) tool to an associated HDL specification is of critical importance to design teams. This paper will develop practical test suite requirements, outline FTL System’s VIVATM technology for automatically generating and applying test suites, and describe the experimental results using VIVA (VHDL Interactive Validation Alchemy) to test FTL Systems’ Auriga ® family of HDL compilers.

Keywords Parallel simulation, hardware description languages, design automation standards, VHDL, VHDL-AMS, Verilog