Abstract

Current interest in ferroelectric thin films stems from the numerous potential device applications for thin films of ferroelectric materials that utilize their unique dielectric, pyroelectric, electro-optic, acousto-optic, and piezo-electric properties. One of the major driving forces in this field is the potential application of ferroelectric thin films for both dynamic random access memory (DRAM) and non-volatile ferroelectric random access memory (FRAM). Ferroelectric lead zirconate titanate (PZT) thin films have gathered considerable attention because of their excellent ferroelectric properties, characterized by high remanent polarization (Pr) and low coercive field (Ec) [1, 2]. Patterning of PZT and electrode materials is one of the key process issues in the integration of these films into silicon devices because they do not easily react with etching gases, and do not form volatile species at low temperature [3, 4]. The ferroelectric film is exposed to high energy photon radiation and energetic ion bombardment during sputtering and reactive ion etching (RIE) of the top electrode for fabrication of integrated ferroelectric capacitors. The radiation and bombardment of the PZT film surface may be enough to modify the top surface layer and thus deform the hysteresis loop [5–7]. PZT films with lower Zr/Ti ratios are considered more attractive, because Ti-rich compositions tend to have lower crystallization temperatures and better squareness of the hysteresis loops [8]. Studies on the deformation in the hystersis loop of PZT films with various Zr/Ti ratios are important for the understanding of ferroelectric properties and the application of ferroelectric thin films. In this letter, we describe the deformation in the hysteresis loop of Pt/PZT/Pt thin film capacitors as a function of Zr/Ti ratios ranging from 60/40 to 20/80. We also explain the effect of top electrode annealing after patterning the Pt top electrode on the ferroelectric properties of Pt/PZT/Pt capacitors. The precursor materials used were lead acetate-3hydrate, zirconium propoxide, and titanium isopropoxide. The precursors with 16% excess lead were synthesized by distilling and reflux in butoxyethanol. The PZT films, 200 nm thick, were prepared using a sol-gel method on the substrate of Pt/Ti/SiO2/Si layers. The thicknesses of the Pt and Ti were 100 and 10 nm, respectively. Prior to spin coating the PZT film, the Pt electrode was annealed at 700 ◦C for 10 min to enhance the adhesion of Pt to SiO2 and the nucleation of the perovskite phase. Sequential spin coating and dry steps were followed by a crystallization for 30 min at 600 ◦C in air. A Pt top electrode with thickness of 80 nm was deposited by d.c. magnetron sputtering without heating the substrate and patterned by RIE using Ar gas for 50 min with resist as a mask. Plasma ashing was done using SF6/O2 gas for 5 min, therefore damage due to the ashing process was negligibly small compared to the RIE process. Details of sputtering and RIE conditions for the Pt electrode have been reported earlier [9]. The Pt/PZT/Pt capacitors were annealed up to 700 ◦C for 10 min after patterning. The polarization-electric field (P-E) hysteresis loop was measured using a modified Sawyer-Tower circuit using a 1 kHz sinusoidal voltage. The small signal capacitance-voltage (C-V ) curves were measured using an HP 4192A low frequency impedance analyzer with an electrode area of 2× 10−4 cm2. The C-V curves were obtained at a frequency of 20 kHz and 50 mV rms signal by sweeping from −5 to +5 V and back again. The structure of the PZT film was measured using X-ray diffraction pattern. All the PZT films were entirely perovskite phase with no detectable pyrochlore or amorphous scattering and had preferential (111) orientation. Subsequent processes such as Pt-sputtering, RIE and annealing did not change the X-ray diffraction pattern. Fig. 1 shows P-E hysteresis loops of PZT (20/80) films for different top electrode annealing temperatures. A large shift of the hysteresis loop along the electrical

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