Zero-Hardened SRAM Cells to Improve Soft Error Tolerance in FPGA

Abstract

Soft errors due to charged particle strikes at the sensitive cell nodes could modify the functionality of the design by changing the configuration bits of an SRAM based FPGA. However, with the development of very-deep-sub-micron (VDSM) or even the nano-technologies, aggressive device size has impacted severely the soft error rate of integrated circuits. In this paper, three new SRAM cell designs are proposed which mainly aim at reducing the soft error rate in FPGA. We verify the soft error tolerance and the power dissipation of these three designs using HSPICE simulation with Berkeley Predictive Technology Model (PTM) of the 65 nm, 1.0 V technology. The simulation results of our three designs are compared with that of standard 6-transistor SRAM cell and an existing increased soft error tolerance cell - ASRAM0. Comparison result shows that our new cells, especially the 0-hardened SRAM cell, have triple the critical charge of the standard 6-transistor SRAM cell, when the cell is storing 0.