Design of a Highly Reliable Low Power Stacked Inverter-Based SRAM Cell with Advanced Self-recoverability from Soft Errors

Abstract

Soft error self-recoverability SRAM cell is designed as an extremely reliable SRAM cell. Because the SRAM cell consists of interior nodes which have a unique feedback mechanism and a larger number of access transistors, it is more expensive than the SESRS cell that is a conventional SRAM cell. has several advantages over standard SRAM cell such as: (1) Single event upsets (SNUs) and double event upsets (DNUs) can be self-recovered. (2) It has the potential to reduce electricity consumption usage by 60.2% and silicon area by 23%, when compared to the only SRAM cell on the market that can self-recover from all types of faults. It also has a fourth low-power double-ended stacked inverters which are used in the cell structure of static random access memory for low power consumption. During hold mode and static mode, the power dissipation is even higher which can be decreased by providing inverters with cross-coupling with a low power supply voltage and power gating. In comparison to the 6 T standard SRAM cell, simulation results in the Tanner EDA v16 program using the 65 nm technology library demonstrate a 47.80% reduction in overall power dissipation, a 20.14% reduction in static power dissipation, and an 83% energy retard product has improved. In comparison to the basic 6 T SRAM cell employing the N-curve methodology, the advanced soft error self-recoverability SRAM cell can speed up read approach time by a percent of 61.83 on total, while the proposed SRAM cell has more write ability.