Workstations (panel discussion)

Abstract

The dynamics of today's electronics industry introduces enormous pressure on chip designers to come up with chip designs in a very limited time. This is due partly to the short life cycle of application specific products in the marketplace. The availability of powerful graphics processors and microprocessors with processing powers comparable to minicomputers has introduced several stand alone workstations into the design arena. Designer productivity is improved to a great extent by the provision of computer-aided design tools that take a product from concept all the way through test at a single design station. This improvement in productivity is very much felt while designing less complex chips. However, corporations that turn out highly complex chips like 32-bit microprocessors and their peripheral chips still rely heavily on the processing powers of powerful mainframes or supercomputers. It is design cases such as these that will question the adequacy and practicability of introducing workstations into the culture of the compcenter-based design methodologies. To them, workstations represent yet another level of computing power which has to be integrated into the design environment.Interestingly enough there is a new breed of machines, namely hardware accelerators, that are specialized to handle some of the most computing intensive steps of the chip design cycle. An example of such a machine is the simulation engine which cuts down the simulation time for large chips by several orders in magnitude. The question is whether these machines can be efficiently interfaced to the workstations thereby providing the increased productivity achievable through a network of workstations and the computing power needed in designing highly complex chips. Does the combination of hardware accelerators and workstations provide an economic and efficient alternative to the best known chip design methodologies, consisting of accurate software CAD tools and main frame computers that have resulted in the state-of-the-art chips?A true workstation is a designer's dream. The requirements on such a dream machine are its user friendliness and the drastic improvement in the designer productivity at an affordable price. Further, it should provide a high degree of mechanization for repetitive tasks as well as have enough computing power to handle the processing intensive steps of the design process. These are the conflicting demands placed on the vendors of today's workstations. Today's workstations, aim at the above goals, but are deficient in answering some of the demands such as simulation for design verification, circuit analysis, fault simulation, test generation and layout analysis of very complex VLSI chips, to name a few. Are these deficiencies real and if so, how can these be overcome in order to provide a workstation that is completely satisfactory to every chip designer? How exactly this will happen and how soon it will happen are some of the questions the panelists will address. The panel consists of the following invitees:Frederick Cohen Mentor Graphics Corp. 8500 SW Creekside Pl. Beaverton, Oregon 97005Steve Law SDA 2461 Mission College Blvd. Santa Clara, California 95054Mark Miller Daisy Corp. 700A Middle field Road Mountain View, California 94039Mike Price Valid Logic 2820 Orchard Pkwy. San Jose, California 95134David Smith Metheus-Computer Vision P. O. Box 1049 Hillsboro, Oregon 97123Nick Van Brunt Zycad Corp. 1315 Redfox Rd. Arden Hills, Minnesota 55112