WL-CSP reliability with various solder alloys and die thicknesses

Abstract

WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back-end processing. A new wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 × 8 array of bumps on a 5 × 5 mm 2 die. The bump structure and package geometry have been optimized using simulation and validated by experimentation. The board used for reliability testing is a 1.2 mm thick, 2-layer FR-4 board with non-soldermask defined landpads with OSP (organic solderability preservative). The landpads are the same diameter as the 250 μm redistribution dielectric via size. Reliability data will be presented for three solder alloys and two wafer thicknesses. The first evaluation compares the reliability of solder alloys SnPbAg and two Pb-free alternatives: SnAgCu and SnCu. The second evaluation evaluates the potential reliability improvement of WL-CSPs by thinning the wafers. Standard thickness WL-CSP wafers are 27-mils. Wafers were thinned down to 4-mils thickness using two techniques. The first method is standard wafer backgrinding. The second is plasma etching, which results in a damage-free surface and improves wafer and die strength.