WITHDRAWN: Design considerations of high linear SAR-ADC for wireless implantable systems

Abstract

Abstract In Wireless Implantable Systems (WIS) linearity is the most prominent performance metric at low frequencies. For data processing in WIS Successive Approximation Register Analog to Digital Converter (SAR-ADC) is used. The SAR-ADC requires Sample and Hold (S/H) circuit, comparator, Successive Approximation Register (SAR), and digital to analog converter. Operational amplifiers are used for designing comparators and S/H circuit. In this SAR-ADC architecture comparator and sample and hold circuit using operational amplifiers was replaced by dynamic latch comparator and a bootstrap circuit which provides less power consumption for battery-operated WIS. This paper reviews different SAR-ADC architectures for low-frequency applications and presents linearity improvement technique in S/H circuit. The 10-bit SAR-ADC was designed in cadence virtuoso in 45nmCMOS technology. Nearly 99% of linearity was achieved with this SAR-ADC architecture.